From 1942a6d111f7af71b36f41dd935992c63ea041a6 Mon Sep 17 00:00:00 2001 From: Scott Murray Date: Thu, 23 May 2024 11:32:52 -0400 Subject: [PATCH] meta-agl-bsp: add bbbappends to fix abseil-cpp RISC-V issue Add dynamically applied abseil-cpp and python3-grpcio bbappends to add backport of the upstream abseil-cpp fix for RISC-V platforms getting SIGILLs. These can be removed when the patches get into upstream meta-oe. Bug-AGL: SPEC-5120 Change-Id: Ib4a918abb3ab57d3ef09dd8729702d0f47d21daa Signed-off-by: Scott Murray Reviewed-on: https://gerrit.automotivelinux.org/gerrit/c/AGL/meta-agl/+/29913 ci-image-build: Jenkins Job builder account Reviewed-by: Jan-Simon Moeller Tested-by: Jenkins Job builder account ci-image-boot-test: Jenkins Job builder account --- ...-unscaledcycleclock-remove-RISC-V-support.patch | 82 ++++++++++++++++++++++ .../abseil-cpp/abseil-cpp_20240116.2.bbappend | 3 + ...-unscaledcycleclock-remove-RISC-V-support.patch | 82 ++++++++++++++++++++++ .../python/python3-grpcio_1.62.%.bbappend | 3 + 4 files changed, 170 insertions(+) create mode 100644 meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch create mode 100644 meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp_20240116.2.bbappend create mode 100644 meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch create mode 100644 meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio_1.62.%.bbappend diff --git a/meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch b/meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch new file mode 100644 index 000000000..461df7a60 --- /dev/null +++ b/meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch @@ -0,0 +1,82 @@ +From 7335a36d0b5c1c597566f9aa3f458a5b6817c3b4 Mon Sep 17 00:00:00 2001 +From: aurel32 +Date: Fri, 22 Mar 2024 14:21:13 -0700 +Subject: [PATCH] PR #1644: unscaledcycleclock: remove RISC-V support + +Imported from GitHub PR https://github.com/abseil/abseil-cpp/pull/1644 + +Starting with Linux 6.6 [1], RDCYCLE is a privileged instruction on RISC-V and can't be used directly from userland. There is a sysctl option to change that as a transition period, but it will eventually disappear. + +The RDTIME instruction is another less accurate alternative, however its frequency varies from board to board, and there is currently now way to get its frequency from userland [2]. + +Therefore this patch just removes the code for unscaledcycleclock on RISC-V. Without processor specific implementation, abseil relies on std::chrono::steady_clock::now().time_since_epoch() which is basically a wrapper around clock_gettime (CLOCK_MONOTONIC), which in turns use __vdso_clock_gettime(). On RISC-V this VDSO is just a wrapper around RDTIME correctly scaled to use nanoseconds units. + +This fixes the testsuite on riscv64, tested on a VisionFive 2 board. + +[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cc4c07c89aada16229084eeb93895c95b7eabaa3 +[2] https://github.com/abseil/abseil-cpp/pull/1631 +Merge 43356a2548cfde76e164d446cb69004b488c6a71 into 76f8011beabdaee872b5fde7546e02407b220cb1 + +Merging this change closes #1644 + +COPYBARA_INTEGRATE_REVIEW=https://github.com/abseil/abseil-cpp/pull/1644 from aurel32:rv64-no-unscaledcycleclock 43356a2548cfde76e164d446cb69004b488c6a71 +PiperOrigin-RevId: 618286262 +Change-Id: Ie4120a727e7d0bb185df6e06ea145c780ebe6652 + +Upstream-Status: Backport [https://github.com/abseil/abseil-cpp/commit/7335a36d] +[Adapted to apply on top of meta-oe's patch stack] +Signed-off-by: Scott Murray +--- + absl/base/internal/unscaledcycleclock.cc | 12 ------------ + absl/base/internal/unscaledcycleclock_config.h | 5 ++--- + 2 files changed, 2 insertions(+), 15 deletions(-) + +diff --git a/absl/base/internal/unscaledcycleclock.cc b/absl/base/internal/unscaledcycleclock.cc +index f11fecb3..103b4f6a 100644 +--- a/absl/base/internal/unscaledcycleclock.cc ++++ b/absl/base/internal/unscaledcycleclock.cc +@@ -121,18 +121,6 @@ double UnscaledCycleClock::Frequency() { + return aarch64_timer_frequency; + } + +-#elif defined(__riscv) +- +-int64_t UnscaledCycleClock::Now() { +- int64_t virtual_timer_value; +- asm volatile("rdcycle %0" : "=r"(virtual_timer_value)); +- return virtual_timer_value; +-} +- +-double UnscaledCycleClock::Frequency() { +- return base_internal::NominalCPUFrequency(); +-} +- + #elif defined(_M_IX86) || defined(_M_X64) + + #pragma intrinsic(__rdtsc) +diff --git a/absl/base/internal/unscaledcycleclock_config.h b/absl/base/internal/unscaledcycleclock_config.h +index 5e232c1a..83552fc5 100644 +--- a/absl/base/internal/unscaledcycleclock_config.h ++++ b/absl/base/internal/unscaledcycleclock_config.h +@@ -22,7 +22,6 @@ + // The following platforms have an implementation of a hardware counter. + #if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) || \ + ((defined(__powerpc__) || defined(__ppc__)) && defined(__GLIBC__)) || \ +- defined(__riscv) || \ + defined(_M_IX86) || (defined(_M_X64) && !defined(_M_ARM64EC)) + #define ABSL_HAVE_UNSCALED_CYCLECLOCK_IMPLEMENTATION 1 + #else +@@ -54,8 +53,8 @@ + #if ABSL_USE_UNSCALED_CYCLECLOCK + // This macro can be used to test if UnscaledCycleClock::Frequency() + // is NominalCPUFrequency() on a particular platform. +-#if (defined(__i386__) || defined(__x86_64__) || defined(__riscv) || \ +- defined(_M_IX86) || defined(_M_X64)) ++#if (defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || \ ++ defined(_M_X64)) + #define ABSL_INTERNAL_UNSCALED_CYCLECLOCK_FREQUENCY_IS_CPU_FREQUENCY + #endif + #endif +-- +2.44.0 + diff --git a/meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp_20240116.2.bbappend b/meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp_20240116.2.bbappend new file mode 100644 index 000000000..2bf47126f --- /dev/null +++ b/meta-agl-bsp/openembedded-layer/recipes-devtools/abseil-cpp/abseil-cpp_20240116.2.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}:" + +SRC_URI += "file://0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch" diff --git a/meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch b/meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch new file mode 100644 index 000000000..82f15f88c --- /dev/null +++ b/meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio/0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch @@ -0,0 +1,82 @@ +From 7335a36d0b5c1c597566f9aa3f458a5b6817c3b4 Mon Sep 17 00:00:00 2001 +From: aurel32 +Date: Fri, 22 Mar 2024 14:21:13 -0700 +Subject: [PATCH] PR #1644: unscaledcycleclock: remove RISC-V support + +Imported from GitHub PR https://github.com/abseil/abseil-cpp/pull/1644 + +Starting with Linux 6.6 [1], RDCYCLE is a privileged instruction on RISC-V and can't be used directly from userland. There is a sysctl option to change that as a transition period, but it will eventually disappear. + +The RDTIME instruction is another less accurate alternative, however its frequency varies from board to board, and there is currently now way to get its frequency from userland [2]. + +Therefore this patch just removes the code for unscaledcycleclock on RISC-V. Without processor specific implementation, abseil relies on std::chrono::steady_clock::now().time_since_epoch() which is basically a wrapper around clock_gettime (CLOCK_MONOTONIC), which in turns use __vdso_clock_gettime(). On RISC-V this VDSO is just a wrapper around RDTIME correctly scaled to use nanoseconds units. + +This fixes the testsuite on riscv64, tested on a VisionFive 2 board. + +[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cc4c07c89aada16229084eeb93895c95b7eabaa3 +[2] https://github.com/abseil/abseil-cpp/pull/1631 +Merge 43356a2548cfde76e164d446cb69004b488c6a71 into 76f8011beabdaee872b5fde7546e02407b220cb1 + +Merging this change closes #1644 + +COPYBARA_INTEGRATE_REVIEW=https://github.com/abseil/abseil-cpp/pull/1644 from aurel32:rv64-no-unscaledcycleclock 43356a2548cfde76e164d446cb69004b488c6a71 +PiperOrigin-RevId: 618286262 +Change-Id: Ie4120a727e7d0bb185df6e06ea145c780ebe6652 + +Upstream-Status: Backport [https://github.com/abseil/abseil-cpp/commit/7335a36d] +[Adapted to apply on top of meta-oe's patch stack] +Signed-off-by: Scott Murray +--- + .../absl/base/internal/unscaledcycleclock.cc | 12 ------------ + .../absl/base/internal/unscaledcycleclock_config.h | 5 ++--- + 2 files changed, 2 insertions(+), 15 deletions(-) + +diff --git a/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.cc b/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.cc +index f11fecb..103b4f6 100644 +--- a/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.cc ++++ b/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.cc +@@ -121,18 +121,6 @@ double UnscaledCycleClock::Frequency() { + return aarch64_timer_frequency; + } + +-#elif defined(__riscv) +- +-int64_t UnscaledCycleClock::Now() { +- int64_t virtual_timer_value; +- asm volatile("rdcycle %0" : "=r"(virtual_timer_value)); +- return virtual_timer_value; +-} +- +-double UnscaledCycleClock::Frequency() { +- return base_internal::NominalCPUFrequency(); +-} +- + #elif defined(_M_IX86) || defined(_M_X64) + + #pragma intrinsic(__rdtsc) +diff --git a/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock_config.h b/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock_config.h +index 5e232c1..83552fc 100644 +--- a/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock_config.h ++++ b/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock_config.h +@@ -22,7 +22,6 @@ + // The following platforms have an implementation of a hardware counter. + #if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) || \ + ((defined(__powerpc__) || defined(__ppc__)) && defined(__GLIBC__)) || \ +- defined(__riscv) || \ + defined(_M_IX86) || (defined(_M_X64) && !defined(_M_ARM64EC)) + #define ABSL_HAVE_UNSCALED_CYCLECLOCK_IMPLEMENTATION 1 + #else +@@ -54,8 +53,8 @@ + #if ABSL_USE_UNSCALED_CYCLECLOCK + // This macro can be used to test if UnscaledCycleClock::Frequency() + // is NominalCPUFrequency() on a particular platform. +-#if (defined(__i386__) || defined(__x86_64__) || defined(__riscv) || \ +- defined(_M_IX86) || defined(_M_X64)) ++#if (defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || \ ++ defined(_M_X64)) + #define ABSL_INTERNAL_UNSCALED_CYCLECLOCK_FREQUENCY_IS_CPU_FREQUENCY + #endif + #endif +-- +2.44.0 + diff --git a/meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio_1.62.%.bbappend b/meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio_1.62.%.bbappend new file mode 100644 index 000000000..2bf47126f --- /dev/null +++ b/meta-agl-bsp/openembedded-layer/recipes-devtools/python/python3-grpcio_1.62.%.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/${BPN}:" + +SRC_URI += "file://0001-PR-1644-unscaledcycleclock-remove-RISC-V-support.patch" -- 2.16.6