Add BSP layers for RISC-V boards

[AGL/AGL-repo.git] / default-floating.xml

diff --git a/default-floating.xml b/default-floating.xml
index a4cf5ea..4b3e71a 100644 (file)
--- a/default-floating.xml
+++ b/default-floating.xml
@@ -82,4 +82,10 @@
   <project name="SanCloudLtd/meta-sancloud" path="bsp/meta-sancloud" remote="github" revision="kirkstone"/>
   <project name="EmbeddedAndroid/meta-rtlwifi" path="bsp/meta-rtlwifi" remote="github" revision="master"/>
 
+  <!-- meta-sifive -->
+  <project name="sifive/meta-sifive" path="bsp/meta-sifive" remote="github" revision="master"/>
+
+  <!-- meta-riscv for several risc boards -->
+  <project name="riscv/meta-riscv" path="bsp/meta-riscv" remote="github" revision="master"/>
+
 </manifest>