meta-agl-refhw-gen3/recipes-kernel/linux/files/0002-Add-AGL-reference-hardware-support.patch

   1 From e8df6330789b106821b9bb59177efa8a191adfda Mon Sep 17 00:00:00 2001
   2 From: Scott Murray <scott.murray@konsulko.com>
   3 Date: Tue, 21 Sep 2021 15:45:18 -0400
   4 Subject: [PATCH 2/4] Add AGL reference hardware support
   5
   6 Upstream-Status: pending
   7
   8 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
   9 Signed-off-by: Raquel Medina <raquel.medina@konsulko.com>
  10 [asm330lhh interrupt fix]
  11 Signed-off-by: Hiroyuki Ishii <ishii.hiroyuki002@jp.panasonic.com>
  12 ---
  13  .../boot/dts/renesas/agl-refhw-common.dtsi    | 922 ++++++++++++++++++
  14  .../boot/dts/renesas/r8a77951-agl-refhw.dts   | 392 ++++++++
  15  drivers/media/i2c/adv748x/adv748x-core.c      |  24 +-
  16  3 files changed, 1337 insertions(+), 1 deletion(-)
  17  create mode 100644 arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  18  create mode 100644 arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
  19
  20 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  21 new file mode 100644
  22 index 000000000000..3f6f8d86f76d
  23 --- /dev/null
  24 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  25 @@ -0,0 +1,922 @@
  26 +// SPDX-License-Identifier: GPL-2.0
  27 +/*
  28 + * Device Tree Source for common parts of AGL Reference Hardware board variants
  29 + *
  30 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
  31 + * Copyright (C) 2020 Konsulko Group
  32 + */
  33 +
  34 +/*
  35 + * This file is derived from salvator-common.dtsi
  36 + *
  37 + * It is currently unclear if the modifications made are such that they could
  38 + * be done on top of salvator-common.dtsi to allow removing the duplication.
  39 + * It is likely that the common pieces with salvator-common.dtsi would need to
  40 + * be factored out into a new common file, which is perhaps hard to justify.
  41 + */
  42 +
  43 +/*
  44 + * SSI-AK4613
  45 + *
  46 + * This command is required when Playback/Capture
  47 + *
  48 + *     amixer set "DVC Out" 100%
  49 + *     amixer set "DVC In" 100%
  50 + *
  51 + * You can use Mute
  52 + *
  53 + *     amixer set "DVC Out Mute" on
  54 + *     amixer set "DVC In Mute" on
  55 + *
  56 + * You can use Volume Ramp
  57 + *
  58 + *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  59 + *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  60 + *     amixer set "DVC Out Ramp" on
  61 + *     aplay xxx.wav &
  62 + *     amixer set "DVC Out"  80%  // Volume Down
  63 + *     amixer set "DVC Out" 100%  // Volume Up
  64 + */
  65 +
  66 +#include <dt-bindings/gpio/gpio.h>
  67 +
  68 +/ {
  69 +       aliases {
  70 +               serial0 = &scif2;
  71 +               serial1 = &scif1;
  72 +               serial2 = &scif5;
  73 +               serial3 = &hscif1;
  74 +               serial4 = &hscif0;
  75 +               serial5 = &hscif2;
  76 +               ethernet0 = &avb;
  77 +               mmc0 = &sdhi2;
  78 +               mmc1 = &sdhi0;
  79 +               mmc2 = &sdhi3;
  80 +       };
  81 +
  82 +       chosen {
  83 +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  84 +               stdout-path = "serial0:115200n8";
  85 +       };
  86 +
  87 +       audio_clkout: audio-clkout {
  88 +               /*
  89 +                * This is same as <&rcar_sound 0>
  90 +                * but needed to avoid cs2000/rcar_sound probe dead-lock
  91 +                */
  92 +               compatible = "fixed-clock";
  93 +               #clock-cells = <0>;
  94 +               clock-frequency = <12288000>;
  95 +       };
  96 +
  97 +       avb-mch@ec5a0100 {
  98 +               compatible = "renesas,avb-mch-gen3";
  99 +               reg =   <0 0xec5a0100 0 0x100>;  /* ADG_AVB */
 100 +               reg-name = "adg_avb";
 101 +
 102 +               clocks = <&cpg CPG_MOD 922>;
 103 +               clock-names = "adg";
 104 +               resets = <&cpg 922>;
 105 +       };
 106 +
 107 +       hdmi0-in {
 108 +               compatible = "hdmi-connector";
 109 +               label = "HDMI0 IN";
 110 +               type = "a";
 111 +
 112 +               port {
 113 +                       hdmi_in_con: endpoint {
 114 +                               remote-endpoint = <&adv7481_hdmi>;
 115 +                       };
 116 +               };
 117 +       };
 118 +
 119 +       hdmi2-in {
 120 +               compatible = "hdmi-connector";
 121 +               label = "HDMI2 IN";
 122 +               type = "a";
 123 +
 124 +               port {
 125 +                       hdmi_in_con2: endpoint {
 126 +                               remote-endpoint = <&adv7481_hdmi2>;
 127 +                       };
 128 +               };
 129 +       };
 130 +
 131 +       reg_1p8v: regulator0 {
 132 +               compatible = "regulator-fixed";
 133 +               regulator-name = "fixed-1.8V";
 134 +               regulator-min-microvolt = <1800000>;
 135 +               regulator-max-microvolt = <1800000>;
 136 +               regulator-boot-on;
 137 +               regulator-always-on;
 138 +       };
 139 +
 140 +       reg_3p3v: regulator1 {
 141 +               compatible = "regulator-fixed";
 142 +               regulator-name = "fixed-3.3V";
 143 +               regulator-min-microvolt = <3300000>;
 144 +               regulator-max-microvolt = <3300000>;
 145 +               regulator-boot-on;
 146 +               regulator-always-on;
 147 +       };
 148 +
 149 +       reg_12v: regulator2 {
 150 +               compatible = "regulator-fixed";
 151 +               regulator-name = "fixed-12V";
 152 +               regulator-min-microvolt = <12000000>;
 153 +               regulator-max-microvolt = <12000000>;
 154 +               regulator-boot-on;
 155 +               regulator-always-on;
 156 +       };
 157 +
 158 +       sound_card: sound {
 159 +               compatible = "audio-graph-card";
 160 +
 161 +               label = "ak4613";
 162 +
 163 +               dais = <&rsnd_port0>;
 164 +       };
 165 +
 166 +       vcc_sdhi0: regulator-vcc-sdhi0 {
 167 +               compatible = "regulator-fixed";
 168 +
 169 +               regulator-name = "SDHI0 Vcc";
 170 +               regulator-min-microvolt = <3300000>;
 171 +               regulator-max-microvolt = <3300000>;
 172 +
 173 +               gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 174 +               enable-active-high;
 175 +       };
 176 +
 177 +       vccq_sdhi0: regulator-vccq-sdhi0 {
 178 +               compatible = "regulator-gpio";
 179 +
 180 +               regulator-name = "SDHI0 VccQ";
 181 +               regulator-min-microvolt = <1800000>;
 182 +               regulator-max-microvolt = <3300000>;
 183 +
 184 +               gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 185 +               gpios-states = <1>;
 186 +               states = <3300000 1
 187 +                         1800000 0>;
 188 +       };
 189 +
 190 +       vcc_sdhi3: regulator-vcc-sdhi3 {
 191 +               compatible = "regulator-fixed";
 192 +
 193 +               regulator-name = "SDHI3 Vcc";
 194 +               regulator-min-microvolt = <3300000>;
 195 +               regulator-max-microvolt = <3300000>;
 196 +
 197 +               gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 198 +               enable-active-high;
 199 +       };
 200 +
 201 +       vccq_sdhi3: regulator-vccq-sdhi3 {
 202 +               compatible = "regulator-gpio";
 203 +
 204 +               regulator-name = "SDHI3 VccQ";
 205 +               regulator-min-microvolt = <1800000>;
 206 +               regulator-max-microvolt = <3300000>;
 207 +
 208 +               gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 209 +               gpios-states = <1>;
 210 +               states = <3300000 1
 211 +                         1800000 0>;
 212 +       };
 213 +
 214 +       hdmi0-out {
 215 +               compatible = "hdmi-connector";
 216 +               label = "HDMI0 OUT";
 217 +               type = "a";
 218 +
 219 +               port {
 220 +                       hdmi0_con: endpoint {
 221 +                       };
 222 +               };
 223 +       };
 224 +
 225 +       hdmi1-out {
 226 +               compatible = "hdmi-connector";
 227 +               label = "HDMI1 OUT";
 228 +               type = "a";
 229 +
 230 +               port {
 231 +                       hdmi1_con: endpoint {
 232 +                       };
 233 +               };
 234 +       };
 235 +
 236 +       x12_clk: x12 {
 237 +               compatible = "fixed-clock";
 238 +               #clock-cells = <0>;
 239 +               clock-frequency = <24576000>;
 240 +       };
 241 +
 242 +       /* External DU dot clocks */
 243 +       x21_clk: x21-clock {
 244 +               compatible = "fixed-clock";
 245 +               #clock-cells = <0>;
 246 +               clock-frequency = <33000000>;
 247 +       };
 248 +
 249 +       x22_clk: x22-clock {
 250 +               compatible = "fixed-clock";
 251 +               #clock-cells = <0>;
 252 +               clock-frequency = <33000000>;
 253 +       };
 254 +
 255 +       x23_clk: x23-clock {
 256 +               compatible = "fixed-clock";
 257 +               #clock-cells = <0>;
 258 +               clock-frequency = <25000000>;
 259 +       };
 260 +};
 261 +
 262 +&a57_0 {
 263 +       cpu-supply = <&dvfs>;
 264 +};
 265 +
 266 +&audio_clk_a {
 267 +       clock-frequency = <22579200>;
 268 +};
 269 +
 270 +&avb {
 271 +       pinctrl-0 = <&avb_pins>;
 272 +       pinctrl-names = "default";
 273 +       phy-handle = <&phy0>;
 274 +       phy-mode = "rgmii-txid";
 275 +       status = "okay";
 276 +
 277 +       phy0: ethernet-phy@0 {
 278 +               rxc-skew-ps = <1500>;
 279 +               reg = <0>;
 280 +               interrupt-parent = <&gpio2>;
 281 +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 282 +               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 283 +       };
 284 +};
 285 +
 286 +&csi40 {
 287 +       status = "okay";
 288 +
 289 +       ports {
 290 +               port@0 {
 291 +                       reg = <0>;
 292 +
 293 +                       csi40_in: endpoint {
 294 +                               clock-lanes = <0>;
 295 +                               data-lanes = <1 2 3 4>;
 296 +                               remote-endpoint = <&adv7481_txa>;
 297 +                       };
 298 +               };
 299 +       };
 300 +};
 301 +
 302 +&csi41 {
 303 +       status = "okay";
 304 +
 305 +       ports {
 306 +               port@0 {
 307 +                       reg = <0>;
 308 +
 309 +                       csi41_in: endpoint {
 310 +                               clock-lanes = <0>;
 311 +                               data-lanes = <1 2 3 4>;
 312 +                               remote-endpoint = <&adv7481_txa2>;
 313 +                       };
 314 +               };
 315 +       };
 316 +};
 317 +
 318 +&du {
 319 +       status = "okay";
 320 +
 321 +};
 322 +
 323 +&ehci0 {
 324 +       dr_mode = "otg";
 325 +       status = "okay";
 326 +};
 327 +
 328 +&ehci1 {
 329 +       status = "okay";
 330 +};
 331 +
 332 +&extalr_clk {
 333 +       clock-frequency = <32768>;
 334 +};
 335 +
 336 +&hscif0 {
 337 +       pinctrl-0 = <&hscif0_pins>;
 338 +       pinctrl-names = "default";
 339 +       uart-has-rtscts;
 340 +
 341 +       status = "okay";
 342 +};
 343 +
 344 +&hscif1 {
 345 +       pinctrl-0 = <&hscif1_pins>;
 346 +       pinctrl-names = "default";
 347 +
 348 +       /* Please use exclusively to the scif1 node */
 349 +       status = "okay";
 350 +};
 351 +
 352 +&hscif2 {
 353 +       pinctrl-0 = <&hscif2_pins>;
 354 +       pinctrl-names = "default";
 355 +
 356 +       status = "okay";
 357 +};
 358 +
 359 +&hsusb {
 360 +       dr_mode = "otg";
 361 +       status = "okay";
 362 +};
 363 +
 364 +&i2c2 {
 365 +       pinctrl-0 = <&i2c2_pins>;
 366 +       pinctrl-names = "default";
 367 +
 368 +       status = "okay";
 369 +
 370 +       clock-frequency = <100000>;
 371 +
 372 +       video-receiver@70 {
 373 +               compatible = "adi,adv7481";
 374 +               reg = <0x70 0x26 0x22 0x34 0x36 0x32
 375 +                      0x31 0x30 0x41 0x79 0x4a 0x48>;
 376 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 377 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 378 +
 379 +               #address-cells = <1>;
 380 +               #size-cells = <0>;
 381 +
 382 +               interrupt-parent = <&gpio0>;
 383 +               interrupt-names = "intrq1", "intrq3";
 384 +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
 385 +                            <5 IRQ_TYPE_LEVEL_LOW>;
 386 +
 387 +               port@8 {
 388 +                       reg = <8>;
 389 +
 390 +                       adv7481_hdmi: endpoint {
 391 +                               remote-endpoint = <&hdmi_in_con>;
 392 +                       };
 393 +               };
 394 +
 395 +               port@a {
 396 +                       reg = <10>;
 397 +
 398 +                       adv7481_txa: endpoint {
 399 +                               clock-lanes = <0>;
 400 +                               data-lanes = <1 2 3 4>;
 401 +                               remote-endpoint = <&csi40_in>;
 402 +                       };
 403 +               };
 404 +
 405 +       };
 406 +
 407 +       video-receiver@71 {
 408 +               compatible = "adi,adv7481";
 409 +               reg = <0x71 0x27 0x23 0x35 0x37 0x33
 410 +                      0x28 0x29 0x42 0x78 0x4b 0x49>;
 411 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 412 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 413 +
 414 +               #address-cells = <1>;
 415 +               #size-cells = <0>;
 416 +
 417 +               interrupt-parent = <&gpio6>;
 418 +               interrupt-names = "intrq1", "intrq3";
 419 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
 420 +                            <1 IRQ_TYPE_LEVEL_LOW>;
 421 +
 422 +               port@8 {
 423 +                       reg = <8>;
 424 +
 425 +                       adv7481_hdmi2: endpoint {
 426 +                               remote-endpoint = <&hdmi_in_con2>;
 427 +                       };
 428 +               };
 429 +
 430 +               port@a {
 431 +                       reg = <10>;
 432 +
 433 +                       adv7481_txa2: endpoint {
 434 +                               clock-lanes = <0>;
 435 +                               data-lanes = <1 2 3 4>;
 436 +                               remote-endpoint = <&csi41_in>;
 437 +                       };
 438 +               };
 439 +       };
 440 +
 441 +       cs2000: clk_multiplier@4f {
 442 +               #clock-cells = <0>;
 443 +               compatible = "cirrus,cs2000-cp";
 444 +               reg = <0x4f>;
 445 +               clocks = <&audio_clkout>, <&x12_clk>;
 446 +               clock-names = "clk_in", "ref_clk";
 447 +
 448 +               assigned-clocks = <&cs2000>;
 449 +               assigned-clock-rates = <24576000>; /* 1/1 divide */
 450 +       };
 451 +};
 452 +
 453 +&i2c3 {
 454 +       pinctrl-0 = <&i2c3_pins>;
 455 +       pinctrl-names = "default";
 456 +
 457 +       status = "okay";
 458 +
 459 +       clock-frequency = <400000>;
 460 +
 461 +       asm330lhh@6a {
 462 +               compatible = "st,asm330lhh";
 463 +               reg = <0x6a>;
 464 +
 465 +               interrupt-names = "int1", "int2";
 466 +               interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
 467 +                                     <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
 468 +               st,drdy-int-pin = <1>;
 469 +       };
 470 +};
 471 +
 472 +&i2c4 {
 473 +       status = "okay";
 474 +
 475 +       versaclock5: clock-generator@68 {
 476 +               compatible = "idt,9fgv0841";
 477 +               reg = <0x68>;
 478 +               #clock-cells = <1>;
 479 +               clocks = <&x23_clk>;
 480 +               clock-names = "xin";
 481 +       };
 482 +};
 483 +
 484 +&i2c5 {
 485 +       pinctrl-0 = <&i2c5_pins>;
 486 +       pinctrl-names = "default";
 487 +
 488 +       status = "okay";
 489 +
 490 +       clock-frequency = <100000>;
 491 +
 492 +       ak4613: codec@10 {
 493 +               compatible = "asahi-kasei,ak4613";
 494 +               #sound-dai-cells = <0>;
 495 +               reg = <0x10>;
 496 +               clocks = <&rcar_sound 3>;
 497 +
 498 +               asahi-kasei,in1-single-end;
 499 +               asahi-kasei,in2-single-end;
 500 +               asahi-kasei,out1-single-end;
 501 +               asahi-kasei,out2-single-end;
 502 +               asahi-kasei,out3-single-end;
 503 +               asahi-kasei,out4-single-end;
 504 +               asahi-kasei,out5-single-end;
 505 +               asahi-kasei,out6-single-end;
 506 +
 507 +               port {
 508 +                       ak4613_endpoint: endpoint {
 509 +                               remote-endpoint = <&rsnd_endpoint0>;
 510 +                       };
 511 +               };
 512 +       };
 513 +};
 514 +
 515 +&i2c_dvfs {
 516 +       status = "okay";
 517 +
 518 +       clock-frequency = <400000>;
 519 +
 520 +       pmic: pmic@30 {
 521 +               pinctrl-0 = <&irq0_pins>;
 522 +               pinctrl-names = "default";
 523 +
 524 +               compatible = "rohm,bd9571mwv";
 525 +               reg = <0x30>;
 526 +               interrupt-parent = <&intc_ex>;
 527 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 528 +               interrupt-controller;
 529 +               #interrupt-cells = <2>;
 530 +               gpio-controller;
 531 +               #gpio-cells = <2>;
 532 +               rohm,ddr-backup-power = <0xf>;
 533 +               rohm,rstbmode-level;
 534 +
 535 +               regulators {
 536 +                       dvfs: dvfs {
 537 +                               regulator-name = "dvfs";
 538 +                               regulator-min-microvolt = <750000>;
 539 +                               regulator-max-microvolt = <1030000>;
 540 +                               regulator-boot-on;
 541 +                               regulator-always-on;
 542 +                       };
 543 +               };
 544 +       };
 545 +
 546 +       eeprom@50 {
 547 +               compatible = "rohm,br24t01", "atmel,24c01";
 548 +               reg = <0x50>;
 549 +               pagesize = <8>;
 550 +       };
 551 +};
 552 +
 553 +&ohci0 {
 554 +       dr_mode = "otg";
 555 +       status = "okay";
 556 +};
 557 +
 558 +&ohci1 {
 559 +       status = "okay";
 560 +};
 561 +
 562 +&pcie_bus_clk {
 563 +       clock-frequency = <100000000>;
 564 +       status = "okay";
 565 +};
 566 +
 567 +&pciec0 {
 568 +       status = "okay";
 569 +};
 570 +
 571 +&pciec1 {
 572 +       status = "okay";
 573 +};
 574 +
 575 +&canfd {
 576 +       pinctrl-0 = <&canfd0_pins &canfd1_pins>;
 577 +       pinctrl-names = "default";
 578 +
 579 +       status = "okay";
 580 +
 581 +       channel0 {
 582 +               status = "okay";
 583 +       };
 584 +
 585 +       channel1 {
 586 +               status = "okay";
 587 +       };
 588 +};
 589 +
 590 +&pfc {
 591 +       pinctrl-0 = <&scif_clk_pins>;
 592 +       pinctrl-names = "default";
 593 +
 594 +       avb_pins: avb {
 595 +               mux {
 596 +                       groups = "avb_link", "avb_mdio", "avb_mii";
 597 +                       function = "avb";
 598 +               };
 599 +
 600 +               pins_mdio {
 601 +                       groups = "avb_mdio";
 602 +                       drive-strength = <24>;
 603 +               };
 604 +
 605 +               pins_mii_tx {
 606 +                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 607 +                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 608 +                       drive-strength = <12>;
 609 +               };
 610 +       };
 611 +
 612 +       hscif0_pins: hscif0 {
 613 +               groups = "hscif0_data", "hscif0_ctrl";
 614 +               function = "hscif0";
 615 +       };
 616 +
 617 +       hscif1_pins: hscif1 {
 618 +               groups = "hscif1_data_a";
 619 +               function = "hscif1";
 620 +       };
 621 +
 622 +       hscif2_pins: hscif2 {
 623 +               groups = "hscif2_data_c";
 624 +               function = "hscif2";
 625 +       };
 626 +
 627 +       i2c2_pins: i2c2 {
 628 +               groups = "i2c2_a";
 629 +               function = "i2c2";
 630 +       };
 631 +
 632 +       i2c3_pins: i2c3 {
 633 +               groups = "i2c3";
 634 +               function = "i2c3";
 635 +       };
 636 +
 637 +       i2c5_pins: i2c5 {
 638 +               groups = "i2c5";
 639 +               function = "i2c5";
 640 +       };
 641 +
 642 +       irq0_pins: irq0 {
 643 +               groups = "intc_ex_irq0";
 644 +               function = "intc_ex";
 645 +       };
 646 +
 647 +       scif1_pins: scif1 {
 648 +               groups = "scif1_data_b";
 649 +               function = "scif1";
 650 +       };
 651 +
 652 +       scif2_pins: scif2 {
 653 +               groups = "scif2_data_a";
 654 +               function = "scif2";
 655 +       };
 656 +
 657 +       scif5_pins: scif5 {
 658 +               groups = "scif5_data_a";
 659 +               function = "scif5";
 660 +       };
 661 +
 662 +       scif_clk_pins: scif_clk {
 663 +               groups = "scif_clk_a";
 664 +               function = "scif_clk";
 665 +       };
 666 +
 667 +       sdhi0_pins: sd0 {
 668 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 669 +               function = "sdhi0";
 670 +               power-source = <3300>;
 671 +       };
 672 +
 673 +       sdhi0_pins_uhs: sd0_uhs {
 674 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 675 +               function = "sdhi0";
 676 +               power-source = <1800>;
 677 +       };
 678 +
 679 +       sdhi2_pins: sd2 {
 680 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 681 +               function = "sdhi2";
 682 +               power-source = <3300>;
 683 +       };
 684 +
 685 +       sdhi2_pins_uhs: sd2_uhs {
 686 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 687 +               function = "sdhi2";
 688 +               power-source = <1800>;
 689 +       };
 690 +
 691 +       sdhi3_pins: sd3 {
 692 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 693 +               function = "sdhi3";
 694 +               power-source = <3300>;
 695 +       };
 696 +
 697 +       sdhi3_pins_uhs: sd3_uhs {
 698 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 699 +               function = "sdhi3";
 700 +               power-source = <1800>;
 701 +       };
 702 +
 703 +       sound_pins: sound {
 704 +               groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
 705 +               function = "ssi";
 706 +       };
 707 +
 708 +       sound_clk_pins: sound_clk {
 709 +               groups = "audio_clk_a_a", "audio_clk_b_a",
 710 +                        "audio_clkout_a", "audio_clkout3_b";
 711 +               function = "audio_clk";
 712 +       };
 713 +
 714 +       usb0_pins: usb0 {
 715 +               groups = "usb0";
 716 +               function = "usb0";
 717 +       };
 718 +
 719 +       usb1_pins: usb1 {
 720 +               groups = "usb1_ovc";
 721 +               function = "usb1";
 722 +       };
 723 +
 724 +       usb30_pins: usb30 {
 725 +               groups = "usb30", "usb30_ovc";
 726 +               function = "usb30";
 727 +       };
 728 +
 729 +       canfd0_pins: canfd0 {
 730 +               groups = "canfd0_data_a";
 731 +               function = "canfd0";
 732 +       };
 733 +
 734 +       canfd1_pins: canfd1 {
 735 +               groups = "canfd1_data";
 736 +               function = "canfd1";
 737 +       };
 738 +};
 739 +
 740 +&rcar_sound {
 741 +       pinctrl-0 = <&sound_pins &sound_clk_pins>;
 742 +       pinctrl-names = "default";
 743 +
 744 +       /* Single DAI */
 745 +       #sound-dai-cells = <0>;
 746 +
 747 +       /* audio_clkout0/1/2/3 */
 748 +       #clock-cells = <1>;
 749 +       clock-frequency = <12288000 11289600>;
 750 +
 751 +       status = "okay";
 752 +
 753 +       /* update <audio_clk_b> to <cs2000> */
 754 +       clocks = <&cpg CPG_MOD 1005>,
 755 +                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 756 +                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 757 +                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 758 +                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 759 +                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 760 +                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 761 +                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 762 +                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 763 +                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 764 +                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 765 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 766 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 767 +                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 768 +                <&audio_clk_a>, <&cs2000>,
 769 +                <&audio_clk_c>,
 770 +                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
 771 +
 772 +       ports {
 773 +               #address-cells = <1>;
 774 +               #size-cells = <0>;
 775 +               rsnd_port0: port@0 {
 776 +                       reg = <0>;
 777 +                       rsnd_endpoint0: endpoint {
 778 +                               remote-endpoint = <&ak4613_endpoint>;
 779 +
 780 +                               dai-format = "left_j";
 781 +                               bitclock-master = <&rsnd_endpoint0>;
 782 +                               frame-master = <&rsnd_endpoint0>;
 783 +
 784 +                               playback = <&ssi3>; //ssi0 -> ssi3
 785 +                               capture  = <&ssi4>; //ssi1 -> ssi4
 786 +                       };
 787 +               };
 788 +       };
 789 +};
 790 +
 791 +&rwdt {
 792 +       timeout-sec = <60>;
 793 +       status = "okay";
 794 +};
 795 +
 796 +&scif1 {
 797 +       pinctrl-0 = <&scif1_pins>;
 798 +       pinctrl-names = "default";
 799 +
 800 +       uart-has-rtscts;
 801 +       /* Please use exclusively to the hscif1 node */
 802 +       status = "okay";
 803 +};
 804 +
 805 +&scif2 {
 806 +       pinctrl-0 = <&scif2_pins>;
 807 +       pinctrl-names = "default";
 808 +
 809 +       status = "okay";
 810 +};
 811 +
 812 +&scif5 {
 813 +       pinctrl-0 = <&scif5_pins>;
 814 +       pinctrl-names = "default";
 815 +
 816 +       status = "okay";
 817 +};
 818 +
 819 +&scif_clk {
 820 +       clock-frequency = <14745600>;
 821 +};
 822 +
 823 +&sdhi0 {
 824 +       pinctrl-0 = <&sdhi0_pins>;
 825 +       pinctrl-1 = <&sdhi0_pins_uhs>;
 826 +       pinctrl-names = "default", "state_uhs";
 827 +
 828 +       vmmc-supply = <&vcc_sdhi0>;
 829 +       vqmmc-supply = <&vccq_sdhi0>;
 830 +       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 831 +       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 832 +       bus-width = <4>;
 833 +       sd-uhs-sdr50;
 834 +       sd-uhs-sdr104;
 835 +       status = "okay";
 836 +};
 837 +
 838 +&sdhi2 {
 839 +       /* used for on-board 8bit eMMC */
 840 +       pinctrl-0 = <&sdhi2_pins>;
 841 +       pinctrl-1 = <&sdhi2_pins_uhs>;
 842 +       pinctrl-names = "default", "state_uhs";
 843 +
 844 +       iommus = <&ipmmu_ds1 34>;
 845 +
 846 +       vmmc-supply = <&reg_3p3v>;
 847 +       vqmmc-supply = <&reg_1p8v>;
 848 +       bus-width = <8>;
 849 +       mmc-hs200-1_8v;
 850 +       mmc-hs400-1_8v;
 851 +       no-sd;
 852 +       no-sdio;
 853 +       non-removable;
 854 +       fixed-emmc-driver-type = <1>;
 855 +       status = "okay";
 856 +};
 857 +
 858 +&sdhi3 {
 859 +       pinctrl-0 = <&sdhi3_pins>;
 860 +       pinctrl-1 = <&sdhi3_pins_uhs>;
 861 +       pinctrl-names = "default", "state_uhs";
 862 +
 863 +       vmmc-supply = <&vcc_sdhi3>;
 864 +       vqmmc-supply = <&vccq_sdhi3>;
 865 +       cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 866 +       wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 867 +       bus-width = <4>;
 868 +       sd-uhs-sdr50;
 869 +       sd-uhs-sdr104;
 870 +       status = "okay";
 871 +};
 872 +
 873 +&ssi4 {
 874 +       shared-pin;
 875 +};
 876 +
 877 +&usb_extal_clk {
 878 +       clock-frequency = <50000000>;
 879 +};
 880 +
 881 +&usb2_phy0 {
 882 +       pinctrl-0 = <&usb0_pins>;
 883 +       pinctrl-names = "default";
 884 +
 885 +       status = "okay";
 886 +};
 887 +
 888 +&usb2_phy1 {
 889 +       pinctrl-0 = <&usb1_pins>;
 890 +       pinctrl-names = "default";
 891 +
 892 +       status = "okay";
 893 +};
 894 +
 895 +&usb3_peri0 {
 896 +       phys = <&usb3_phy0>;
 897 +       phy-names = "usb";
 898 +
 899 +       status = "okay";
 900 +};
 901 +
 902 +&usb3_phy0 {
 903 +       status = "okay";
 904 +};
 905 +
 906 +&usb3s0_clk {
 907 +       clock-frequency = <100000000>;
 908 +};
 909 +
 910 +&vin0 {
 911 +       status = "okay";
 912 +};
 913 +
 914 +&vin1 {
 915 +       status = "okay";
 916 +};
 917 +
 918 +&vin2 {
 919 +       status = "okay";
 920 +};
 921 +
 922 +&vin3 {
 923 +       status = "okay";
 924 +};
 925 +
 926 +&vin4 {
 927 +       status = "okay";
 928 +};
 929 +
 930 +&vin5 {
 931 +       status = "okay";
 932 +};
 933 +
 934 +&vin6 {
 935 +       status = "okay";
 936 +};
 937 +
 938 +&vin7 {
 939 +       status = "okay";
 940 +};
 941 +
 942 +&xhci0 {
 943 +       pinctrl-0 = <&usb30_pins>;
 944 +       pinctrl-names = "default";
 945 +
 946 +       status = "okay";
 947 +};
 948 diff --git a/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
 949 new file mode 100644
 950 index 000000000000..3d1107f6d9cc
 951 --- /dev/null
 952 +++ b/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
 953 @@ -0,0 +1,392 @@
 954 +/*
 955 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
 956 + *
 957 + * Copyright (C) 2019 Panasonic Corp.
 958 + * Copyright (C) 2020 Konsulko Group
 959 + *
 960 + * This file is licensed under the terms of the GNU General Public License
 961 + * version 2.  This program is licensed "as is" without any warranty of any
 962 + * kind, whether express or implied.
 963 + */
 964 +
 965 +/*
 966 + * This file is for the most part derived from:
 967 + *
 968 + * - r8a77951-salvator-xs-4x2g.dts
 969 + * - r8a77951-salvator-xs.dts
 970 + * - salvator-xs.dtsi
 971 + *
 972 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
 973 + */
 974 +
 975 +/dts-v1/;
 976 +#include "r8a77951.dtsi"
 977 +#include "agl-refhw-common.dtsi"
 978 +
 979 +/ {
 980 +       model = "AGL Reference Hardware based on r8a77951 ES3.0+ with 8GiB (4 x 2 GiB)";
 981 +       compatible = "agl,refhw-h3", "renesas,r8a7795";
 982 +
 983 +       memory@48000000 {
 984 +               device_type = "memory";
 985 +               /* first 128MB is reserved for secure area. */
 986 +               reg = <0x0 0x48000000 0x0 0x78000000>;
 987 +       };
 988 +
 989 +       memory@500000000 {
 990 +               device_type = "memory";
 991 +               reg = <0x5 0x00000000 0x0 0x80000000>;
 992 +       };
 993 +
 994 +       memory@600000000 {
 995 +               device_type = "memory";
 996 +               reg = <0x6 0x00000000 0x0 0x80000000>;
 997 +       };
 998 +
 999 +       memory@700000000 {
1000 +               device_type = "memory";
1001 +               reg = <0x7 0x00000000 0x0 0x80000000>;
1002 +       };
1003 +
1004 +       reserved-memory {
1005 +               #address-cells = <2>;
1006 +               #size-cells = <2>;
1007 +               ranges;
1008 +
1009 +               /* device specific region for Lossy Decompression */
1010 +               lossy_decompress: linux,lossy_decompress@54000000 {
1011 +                       no-map;
1012 +                       reg = <0x00000000 0x54000000 0x0 0x03000000>;
1013 +               };
1014 +
1015 +               /* For Audio DSP */
1016 +               adsp_reserved: linux,adsp@57000000 {
1017 +                       compatible = "shared-dma-pool";
1018 +                       reusable;
1019 +                       reg = <0x00000000 0x57000000 0x0 0x01000000>;
1020 +               };
1021 +
1022 +               /* global autoconfigured region for contiguous allocations */
1023 +               linux,cma@58000000 {
1024 +                       compatible = "shared-dma-pool";
1025 +                       reusable;
1026 +                       reg = <0x00000000 0x58000000 0x0 0x18000000>;
1027 +                       linux,cma-default;
1028 +               };
1029 +
1030 +               /* device specific region for contiguous allocations */
1031 +               mmp_reserved: linux,multimedia@70000000 {
1032 +                       compatible = "shared-dma-pool";
1033 +                       reusable;
1034 +                       reg = <0x00000000 0x70000000 0x0 0x10000000>;
1035 +               };
1036 +       };
1037 +
1038 +       mmngr {
1039 +               compatible = "renesas,mmngr";
1040 +               memory-region = <&mmp_reserved>, <&lossy_decompress>;
1041 +       };
1042 +
1043 +       mmngrbuf {
1044 +               compatible = "renesas,mmngrbuf";
1045 +       };
1046 +
1047 +       vspm_if {
1048 +               compatible = "renesas,vspm_if";
1049 +       };
1050 +
1051 +       vga {
1052 +               port {
1053 +                       vga_in: endpoint {
1054 +                               /delete-property/remote-endpoint;
1055 +                       };
1056 +               };
1057 +       };
1058 +
1059 +       vga-encoder {
1060 +               ports {
1061 +                       port@0 {
1062 +                               adv7123_in: endpoint {
1063 +                                       /delete-property/remote-endpoint;
1064 +                               };
1065 +                       };
1066 +
1067 +                       port@1 {
1068 +                               adv7123_out: endpoint {
1069 +                                       /delete-property/remote-endpoint;
1070 +                               };
1071 +                       };
1072 +               };
1073 +       };
1074 +
1075 +};
1076 +
1077 +&adsp {
1078 +       status = "okay";
1079 +       memory-region = <&adsp_reserved>;
1080 +};
1081 +
1082 +&du {
1083 +       clocks = <&cpg CPG_MOD 724>,
1084 +                <&cpg CPG_MOD 723>,
1085 +                <&cpg CPG_MOD 722>,
1086 +                <&cpg CPG_MOD 721>,
1087 +                <&versaclock6 1>,
1088 +                <&x21_clk>,
1089 +                <&x22_clk>,
1090 +                <&versaclock6 2>;
1091 +       clock-names = "du.0", "du.1", "du.2", "du.3",
1092 +                     "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1093 +};
1094 +
1095 +&ehci2 {
1096 +       status = "okay";
1097 +};
1098 +
1099 +&ehci3 {
1100 +       dr_mode = "otg";
1101 +       status = "okay";
1102 +};
1103 +
1104 +&hsusb3 {
1105 +       dr_mode = "otg";
1106 +       status = "okay";
1107 +};
1108 +
1109 +&sound_card {
1110 +       dais = <&rsnd_port0     /* ak4613 */
1111 +               &rsnd_port1     /* HDMI0  */
1112 +               &rsnd_port2>;   /* HDMI1  */
1113 +};
1114 +
1115 +&hdmi0 {
1116 +       status = "okay";
1117 +
1118 +       ports {
1119 +               port@1 {
1120 +                       reg = <1>;
1121 +                       rcar_dw_hdmi0_out: endpoint {
1122 +                               remote-endpoint = <&hdmi0_con>;
1123 +                       };
1124 +               };
1125 +               port@2 {
1126 +                       reg = <2>;
1127 +                       dw_hdmi0_snd_in: endpoint {
1128 +                               remote-endpoint = <&rsnd_endpoint1>;
1129 +                       };
1130 +               };
1131 +       };
1132 +};
1133 +
1134 +&hdmi0_con {
1135 +       remote-endpoint = <&rcar_dw_hdmi0_out>;
1136 +};
1137 +
1138 +&hdmi1 {
1139 +       status = "okay";
1140 +
1141 +       ports {
1142 +               port@1 {
1143 +                       reg = <1>;
1144 +                       rcar_dw_hdmi1_out: endpoint {
1145 +                               remote-endpoint = <&hdmi1_con>;
1146 +                       };
1147 +               };
1148 +               port@2 {
1149 +                       reg = <2>;
1150 +                       dw_hdmi1_snd_in: endpoint {
1151 +                               remote-endpoint = <&rsnd_endpoint2>;
1152 +                       };
1153 +               };
1154 +       };
1155 +};
1156 +
1157 +&hdmi1_con {
1158 +       remote-endpoint = <&rcar_dw_hdmi1_out>;
1159 +};
1160 +
1161 +&ohci2 {
1162 +       status = "okay";
1163 +};
1164 +
1165 +&ohci3 {
1166 +       dr_mode = "otg";
1167 +       status = "okay";
1168 +};
1169 +
1170 +&rcar_sound {
1171 +       ports {
1172 +               /* rsnd_port0 is on salvator-common */
1173 +               rsnd_port1: port@1 {
1174 +                       reg = <1>;
1175 +                       rsnd_endpoint1: endpoint {
1176 +                               remote-endpoint = <&dw_hdmi0_snd_in>;
1177 +
1178 +                               dai-format = "i2s";
1179 +                               bitclock-master = <&rsnd_endpoint1>;
1180 +                               frame-master = <&rsnd_endpoint1>;
1181 +
1182 +                               playback = <&ssi2>;
1183 +                       };
1184 +               };
1185 +               rsnd_port2: port@2 {
1186 +                       reg = <2>;
1187 +                       rsnd_endpoint2: endpoint {
1188 +                               remote-endpoint = <&dw_hdmi1_snd_in>;
1189 +
1190 +                               dai-format = "i2s";
1191 +                               bitclock-master = <&rsnd_endpoint2>;
1192 +                               frame-master = <&rsnd_endpoint2>;
1193 +
1194 +                               playback = <&ssi3>;
1195 +                       };
1196 +               };
1197 +       };
1198 +};
1199 +
1200 +&pfc {
1201 +       usb2_pins: usb2 {
1202 +               groups = "usb2", "usb2_ovc";
1203 +               function = "usb2";
1204 +       };
1205 +
1206 +       /*
1207 +        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1208 +        *   (when SW31 is the default setting on Salvator-XS).
1209 +        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1210 +        *   r8a77951 with Salvator-XS.
1211 +        *   Hence the SW31 setting must be changed like 2) below.
1212 +        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1213 +        *      - Connect GP6_3[01] to ADV7842.
1214 +        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1215 +        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1216 +        *      - Connect GP6_{04,21} to ADV7842.
1217 +        */
1218 +       usb2_ch3_pins: usb2_ch3 {
1219 +               groups = "usb2_ch3";
1220 +               function = "usb2_ch3";
1221 +       };
1222 +};
1223 +
1224 +&usb2_phy2 {
1225 +       pinctrl-0 = <&usb2_pins>;
1226 +       pinctrl-names = "default";
1227 +
1228 +       status = "okay";
1229 +};
1230 +
1231 +&usb2_phy3 {
1232 +       pinctrl-0 = <&usb2_ch3_pins>;
1233 +       pinctrl-names = "default";
1234 +
1235 +       status = "okay";
1236 +};
1237 +
1238 +&vspbc {
1239 +       status = "okay";
1240 +};
1241 +
1242 +&vspbd {
1243 +       status = "okay";
1244 +};
1245 +
1246 +&vspi0 {
1247 +       status = "okay";
1248 +};
1249 +
1250 +&vspi1 {
1251 +       status = "okay";
1252 +};
1253 +
1254 +/* End r8a77951-salvator-xs.dts content */
1255 +
1256 +
1257 +/* Start r8a77951-salvator-xs-4x2g.dts content */
1258 +
1259 +&pciec0 {
1260 +       /* Map all possible DDR as inbound ranges */
1261 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1262 +};
1263 +
1264 +&pciec1 {
1265 +       /* Map all possible DDR as inbound ranges */
1266 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1267 +};
1268 +
1269 +/* End r8a77951-salvator-xs-4x2g.dts content */
1270 +
1271 +
1272 +/* Start salvator-xs.dts content */
1273 +
1274 +&extal_clk {
1275 +       clock-frequency = <16640000>;
1276 +};
1277 +
1278 +&i2c4 {
1279 +       clock-frequency = <400000>;
1280 +
1281 +       versaclock6: clock-generator@6a {
1282 +               compatible = "idt,5p49v6901";
1283 +               reg = <0x6a>;
1284 +               #clock-cells = <1>;
1285 +               clocks = <&x23_clk>;
1286 +               clock-names = "xin";
1287 +       };
1288 +};
1289 +
1290 +/* End salvator-xs.dts content */
1291 +
1292 +
1293 +/* Start reference hardware specific tweaks */
1294 +
1295 +&du {
1296 +       ports {
1297 +               port@0 {
1298 +                       endpoint {
1299 +                               /delete-property/remote-endpoint;
1300 +                       };
1301 +               };
1302 +
1303 +               port@3 {
1304 +                       endpoint {
1305 +                               /delete-property/remote-endpoint;
1306 +                       };
1307 +               };
1308 +       };
1309 +};
1310 +
1311 +&lvds0 {
1312 +       status = "disabled";
1313 +};
1314 +
1315 +&pwm1 {
1316 +       status = "disabled";
1317 +};
1318 +
1319 +&scif_clk {
1320 +       clock-frequency = <0>;
1321 +};
1322 +
1323 +&sdhi0 {
1324 +       /delete-property/ wp-gpios;
1325 +       non-removable;
1326 +};
1327 +
1328 +&sdhi3 {
1329 +       /delete-property/ wp-gpios;
1330 +       non-removable;
1331 +};
1332 +
1333 +&gpio6 {
1334 +       /* Enable the CAN 1 & 2 transceivers */
1335 +       can-1-transceiver-stb {
1336 +               gpio-hog;
1337 +               gpios = <21 GPIO_ACTIVE_HIGH>;
1338 +               output-low;
1339 +       };
1340 +       can-2-transceiver-stb {
1341 +               gpio-hog;
1342 +               gpios = <12 GPIO_ACTIVE_HIGH>;
1343 +               output-low;
1344 +       };
1345 +};
1346 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1347 index fe156e8f88b8..da295b106561 100644
1348 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1349 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1350 @@ -97,6 +97,21 @@ static const struct adv748x_register_map adv748x_default_addresses[] = {
1351         [ADV748X_PAGE_TXA] = { "txa", 0x4a },
1352  };
1353
1354 +static const struct adv748x_register_map adv748x_default_addresses2[] = {
1355 +       [ADV748X_PAGE_IO] = { "main", 0x71 },
1356 +       [ADV748X_PAGE_DPLL] = { "dpll", 0x27 },
1357 +       [ADV748X_PAGE_CP] = { "cp", 0x23 },
1358 +       [ADV748X_PAGE_HDMI] = { "hdmi", 0x35 },
1359 +       [ADV748X_PAGE_EDID] = { "edid", 0x37 },
1360 +       [ADV748X_PAGE_REPEATER] = { "repeater", 0x33 },
1361 +       [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x28 },
1362 +       [ADV748X_PAGE_CBUS] = { "cbus", 0x29 },
1363 +       [ADV748X_PAGE_CEC] = { "cec", 0x42 },
1364 +       [ADV748X_PAGE_SDP] = { "sdp", 0x78 },
1365 +       [ADV748X_PAGE_TXB] = { "txb", 0x49 },
1366 +       [ADV748X_PAGE_TXA] = { "txa", 0x4b },
1367 +};
1368 +
1369  static int adv748x_read_check(struct adv748x_state *state,
1370                               int client_page, u8 reg)
1371  {
1372 @@ -183,10 +198,17 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
1373         int ret;
1374
1375         for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1376 -               state->i2c_clients[i] = i2c_new_ancillary_device(
1377 +               if ((state->client->addr << 1) == 0xe0) {
1378 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1379                                 state->client,
1380                                 adv748x_default_addresses[i].name,
1381                                 adv748x_default_addresses[i].default_addr);
1382 +               } else {
1383 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1384 +                               state->client,
1385 +                               adv748x_default_addresses2[i].name,
1386 +                               adv748x_default_addresses2[i].default_addr);
1387 +               }
1388
1389                 if (IS_ERR(state->i2c_clients[i])) {
1390                         adv_err(state, "failed to create i2c client %u\n", i);
1391 --
1392 2.35.1
1393