meta-agl-refhw-gen3/recipes-kernel/linux/files/0002-Add-AGL-reference-hardware-support.patch

   1 From a544d23becdda2f8fb44506498c57fc46b5a075d Mon Sep 17 00:00:00 2001
   2 From: Scott Murray <scott.murray@konsulko.com>
   3 Date: Tue, 21 Sep 2021 15:45:18 -0400
   4 Subject: [PATCH 2/4] Add AGL reference hardware support
   5
   6 Upstream-Status: pending
   7
   8 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
   9 Signed-off-by: Raquel Medina <raquel.medina@konsulko.com>
  10 [asm330lhh interrupt fix]
  11 Signed-off-by: Hiroyuki Ishii <ishii.hiroyuki002@jp.panasonic.com>
  12 ---
  13  .../boot/dts/renesas/agl-refhw-common.dtsi    | 919 ++++++++++++++++++
  14  .../boot/dts/renesas/r8a77951-agl-refhw.dts   | 392 ++++++++
  15  drivers/media/i2c/adv748x/adv748x-core.c      |  24 +-
  16  3 files changed, 1334 insertions(+), 1 deletion(-)
  17  create mode 100644 arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  18  create mode 100644 arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
  19
  20 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  21 new file mode 100644
  22 index 000000000000..7474ed578c21
  23 --- /dev/null
  24 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  25 @@ -0,0 +1,919 @@
  26 +// SPDX-License-Identifier: GPL-2.0
  27 +/*
  28 + * Device Tree Source for common parts of AGL Reference Hardware board variants
  29 + *
  30 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
  31 + * Copyright (C) 2020 Konsulko Group
  32 + */
  33 +
  34 +/*
  35 + * This file is derived from salvator-common.dtsi
  36 + *
  37 + * It is currently unclear if the modifications made are such that they could
  38 + * be done on top of salvator-common.dtsi to allow removing the duplication.
  39 + * It is likely that the common pieces with salvator-common.dtsi would need to
  40 + * be factored out into a new common file, which is perhaps hard to justify.
  41 + */
  42 +
  43 +/*
  44 + * SSI-AK4613
  45 + *
  46 + * This command is required when Playback/Capture
  47 + *
  48 + *     amixer set "DVC Out" 100%
  49 + *     amixer set "DVC In" 100%
  50 + *
  51 + * You can use Mute
  52 + *
  53 + *     amixer set "DVC Out Mute" on
  54 + *     amixer set "DVC In Mute" on
  55 + *
  56 + * You can use Volume Ramp
  57 + *
  58 + *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  59 + *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  60 + *     amixer set "DVC Out Ramp" on
  61 + *     aplay xxx.wav &
  62 + *     amixer set "DVC Out"  80%  // Volume Down
  63 + *     amixer set "DVC Out" 100%  // Volume Up
  64 + */
  65 +
  66 +#include <dt-bindings/gpio/gpio.h>
  67 +
  68 +/ {
  69 +       aliases {
  70 +               serial0 = &scif2;
  71 +               serial1 = &scif1;
  72 +               serial2 = &scif5;
  73 +               serial3 = &hscif1;
  74 +               serial4 = &hscif0;
  75 +               serial5 = &hscif2;
  76 +               ethernet0 = &avb;
  77 +       };
  78 +
  79 +       chosen {
  80 +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  81 +               stdout-path = "serial0:115200n8";
  82 +       };
  83 +
  84 +       audio_clkout: audio-clkout {
  85 +               /*
  86 +                * This is same as <&rcar_sound 0>
  87 +                * but needed to avoid cs2000/rcar_sound probe dead-lock
  88 +                */
  89 +               compatible = "fixed-clock";
  90 +               #clock-cells = <0>;
  91 +               clock-frequency = <12288000>;
  92 +       };
  93 +
  94 +       avb-mch@ec5a0100 {
  95 +               compatible = "renesas,avb-mch-gen3";
  96 +               reg =   <0 0xec5a0100 0 0x100>;  /* ADG_AVB */
  97 +               reg-name = "adg_avb";
  98 +
  99 +               clocks = <&cpg CPG_MOD 922>;
 100 +               clock-names = "adg";
 101 +               resets = <&cpg 922>;
 102 +       };
 103 +
 104 +       hdmi0-in {
 105 +               compatible = "hdmi-connector";
 106 +               label = "HDMI0 IN";
 107 +               type = "a";
 108 +
 109 +               port {
 110 +                       hdmi_in_con: endpoint {
 111 +                               remote-endpoint = <&adv7481_hdmi>;
 112 +                       };
 113 +               };
 114 +       };
 115 +
 116 +       hdmi2-in {
 117 +               compatible = "hdmi-connector";
 118 +               label = "HDMI2 IN";
 119 +               type = "a";
 120 +
 121 +               port {
 122 +                       hdmi_in_con2: endpoint {
 123 +                               remote-endpoint = <&adv7481_hdmi2>;
 124 +                       };
 125 +               };
 126 +       };
 127 +
 128 +       reg_1p8v: regulator0 {
 129 +               compatible = "regulator-fixed";
 130 +               regulator-name = "fixed-1.8V";
 131 +               regulator-min-microvolt = <1800000>;
 132 +               regulator-max-microvolt = <1800000>;
 133 +               regulator-boot-on;
 134 +               regulator-always-on;
 135 +       };
 136 +
 137 +       reg_3p3v: regulator1 {
 138 +               compatible = "regulator-fixed";
 139 +               regulator-name = "fixed-3.3V";
 140 +               regulator-min-microvolt = <3300000>;
 141 +               regulator-max-microvolt = <3300000>;
 142 +               regulator-boot-on;
 143 +               regulator-always-on;
 144 +       };
 145 +
 146 +       reg_12v: regulator2 {
 147 +               compatible = "regulator-fixed";
 148 +               regulator-name = "fixed-12V";
 149 +               regulator-min-microvolt = <12000000>;
 150 +               regulator-max-microvolt = <12000000>;
 151 +               regulator-boot-on;
 152 +               regulator-always-on;
 153 +       };
 154 +
 155 +       sound_card: sound {
 156 +               compatible = "audio-graph-card";
 157 +
 158 +               label = "ak4613";
 159 +
 160 +               dais = <&rsnd_port0>;
 161 +       };
 162 +
 163 +       vcc_sdhi0: regulator-vcc-sdhi0 {
 164 +               compatible = "regulator-fixed";
 165 +
 166 +               regulator-name = "SDHI0 Vcc";
 167 +               regulator-min-microvolt = <3300000>;
 168 +               regulator-max-microvolt = <3300000>;
 169 +
 170 +               gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 171 +               enable-active-high;
 172 +       };
 173 +
 174 +       vccq_sdhi0: regulator-vccq-sdhi0 {
 175 +               compatible = "regulator-gpio";
 176 +
 177 +               regulator-name = "SDHI0 VccQ";
 178 +               regulator-min-microvolt = <1800000>;
 179 +               regulator-max-microvolt = <3300000>;
 180 +
 181 +               gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 182 +               gpios-states = <1>;
 183 +               states = <3300000 1
 184 +                         1800000 0>;
 185 +       };
 186 +
 187 +       vcc_sdhi3: regulator-vcc-sdhi3 {
 188 +               compatible = "regulator-fixed";
 189 +
 190 +               regulator-name = "SDHI3 Vcc";
 191 +               regulator-min-microvolt = <3300000>;
 192 +               regulator-max-microvolt = <3300000>;
 193 +
 194 +               gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 195 +               enable-active-high;
 196 +       };
 197 +
 198 +       vccq_sdhi3: regulator-vccq-sdhi3 {
 199 +               compatible = "regulator-gpio";
 200 +
 201 +               regulator-name = "SDHI3 VccQ";
 202 +               regulator-min-microvolt = <1800000>;
 203 +               regulator-max-microvolt = <3300000>;
 204 +
 205 +               gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 206 +               gpios-states = <1>;
 207 +               states = <3300000 1
 208 +                         1800000 0>;
 209 +       };
 210 +
 211 +       hdmi0-out {
 212 +               compatible = "hdmi-connector";
 213 +               label = "HDMI0 OUT";
 214 +               type = "a";
 215 +
 216 +               port {
 217 +                       hdmi0_con: endpoint {
 218 +                       };
 219 +               };
 220 +       };
 221 +
 222 +       hdmi1-out {
 223 +               compatible = "hdmi-connector";
 224 +               label = "HDMI1 OUT";
 225 +               type = "a";
 226 +
 227 +               port {
 228 +                       hdmi1_con: endpoint {
 229 +                       };
 230 +               };
 231 +       };
 232 +
 233 +       x12_clk: x12 {
 234 +               compatible = "fixed-clock";
 235 +               #clock-cells = <0>;
 236 +               clock-frequency = <24576000>;
 237 +       };
 238 +
 239 +       /* External DU dot clocks */
 240 +       x21_clk: x21-clock {
 241 +               compatible = "fixed-clock";
 242 +               #clock-cells = <0>;
 243 +               clock-frequency = <33000000>;
 244 +       };
 245 +
 246 +       x22_clk: x22-clock {
 247 +               compatible = "fixed-clock";
 248 +               #clock-cells = <0>;
 249 +               clock-frequency = <33000000>;
 250 +       };
 251 +
 252 +       x23_clk: x23-clock {
 253 +               compatible = "fixed-clock";
 254 +               #clock-cells = <0>;
 255 +               clock-frequency = <25000000>;
 256 +       };
 257 +};
 258 +
 259 +&a57_0 {
 260 +       cpu-supply = <&dvfs>;
 261 +};
 262 +
 263 +&audio_clk_a {
 264 +       clock-frequency = <22579200>;
 265 +};
 266 +
 267 +&avb {
 268 +       pinctrl-0 = <&avb_pins>;
 269 +       pinctrl-names = "default";
 270 +       phy-handle = <&phy0>;
 271 +       phy-mode = "rgmii-txid";
 272 +       status = "okay";
 273 +
 274 +       phy0: ethernet-phy@0 {
 275 +               rxc-skew-ps = <1500>;
 276 +               reg = <0>;
 277 +               interrupt-parent = <&gpio2>;
 278 +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 279 +               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 280 +       };
 281 +};
 282 +
 283 +&csi40 {
 284 +       status = "okay";
 285 +
 286 +       ports {
 287 +               port@0 {
 288 +                       reg = <0>;
 289 +
 290 +                       csi40_in: endpoint {
 291 +                               clock-lanes = <0>;
 292 +                               data-lanes = <1 2 3 4>;
 293 +                               remote-endpoint = <&adv7481_txa>;
 294 +                       };
 295 +               };
 296 +       };
 297 +};
 298 +
 299 +&csi41 {
 300 +       status = "okay";
 301 +
 302 +       ports {
 303 +               port@0 {
 304 +                       reg = <0>;
 305 +
 306 +                       csi41_in: endpoint {
 307 +                               clock-lanes = <0>;
 308 +                               data-lanes = <1 2 3 4>;
 309 +                               remote-endpoint = <&adv7481_txa2>;
 310 +                       };
 311 +               };
 312 +       };
 313 +};
 314 +
 315 +&du {
 316 +       status = "okay";
 317 +
 318 +};
 319 +
 320 +&ehci0 {
 321 +       dr_mode = "otg";
 322 +       status = "okay";
 323 +};
 324 +
 325 +&ehci1 {
 326 +       status = "okay";
 327 +};
 328 +
 329 +&extalr_clk {
 330 +       clock-frequency = <32768>;
 331 +};
 332 +
 333 +&hscif0 {
 334 +       pinctrl-0 = <&hscif0_pins>;
 335 +       pinctrl-names = "default";
 336 +       uart-has-rtscts;
 337 +
 338 +       status = "okay";
 339 +};
 340 +
 341 +&hscif1 {
 342 +       pinctrl-0 = <&hscif1_pins>;
 343 +       pinctrl-names = "default";
 344 +
 345 +       /* Please use exclusively to the scif1 node */
 346 +       status = "okay";
 347 +};
 348 +
 349 +&hscif2 {
 350 +       pinctrl-0 = <&hscif2_pins>;
 351 +       pinctrl-names = "default";
 352 +
 353 +       status = "okay";
 354 +};
 355 +
 356 +&hsusb {
 357 +       dr_mode = "otg";
 358 +       status = "okay";
 359 +};
 360 +
 361 +&i2c2 {
 362 +       pinctrl-0 = <&i2c2_pins>;
 363 +       pinctrl-names = "default";
 364 +
 365 +       status = "okay";
 366 +
 367 +       clock-frequency = <100000>;
 368 +
 369 +       video-receiver@70 {
 370 +               compatible = "adi,adv7481";
 371 +               reg = <0x70 0x26 0x22 0x34 0x36 0x32
 372 +                      0x31 0x30 0x41 0x79 0x4a 0x48>;
 373 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 374 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 375 +
 376 +               #address-cells = <1>;
 377 +               #size-cells = <0>;
 378 +
 379 +               interrupt-parent = <&gpio0>;
 380 +               interrupt-names = "intrq1", "intrq3";
 381 +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
 382 +                            <5 IRQ_TYPE_LEVEL_LOW>;
 383 +
 384 +               port@8 {
 385 +                       reg = <8>;
 386 +
 387 +                       adv7481_hdmi: endpoint {
 388 +                               remote-endpoint = <&hdmi_in_con>;
 389 +                       };
 390 +               };
 391 +
 392 +               port@a {
 393 +                       reg = <10>;
 394 +
 395 +                       adv7481_txa: endpoint {
 396 +                               clock-lanes = <0>;
 397 +                               data-lanes = <1 2 3 4>;
 398 +                               remote-endpoint = <&csi40_in>;
 399 +                       };
 400 +               };
 401 +
 402 +       };
 403 +
 404 +       video-receiver@71 {
 405 +               compatible = "adi,adv7481";
 406 +               reg = <0x71 0x27 0x23 0x35 0x37 0x33
 407 +                      0x28 0x29 0x42 0x78 0x4b 0x49>;
 408 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 409 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 410 +
 411 +               #address-cells = <1>;
 412 +               #size-cells = <0>;
 413 +
 414 +               interrupt-parent = <&gpio6>;
 415 +               interrupt-names = "intrq1", "intrq3";
 416 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
 417 +                            <1 IRQ_TYPE_LEVEL_LOW>;
 418 +
 419 +               port@8 {
 420 +                       reg = <8>;
 421 +
 422 +                       adv7481_hdmi2: endpoint {
 423 +                               remote-endpoint = <&hdmi_in_con2>;
 424 +                       };
 425 +               };
 426 +
 427 +               port@a {
 428 +                       reg = <10>;
 429 +
 430 +                       adv7481_txa2: endpoint {
 431 +                               clock-lanes = <0>;
 432 +                               data-lanes = <1 2 3 4>;
 433 +                               remote-endpoint = <&csi41_in>;
 434 +                       };
 435 +               };
 436 +       };
 437 +
 438 +       cs2000: clk_multiplier@4f {
 439 +               #clock-cells = <0>;
 440 +               compatible = "cirrus,cs2000-cp";
 441 +               reg = <0x4f>;
 442 +               clocks = <&audio_clkout>, <&x12_clk>;
 443 +               clock-names = "clk_in", "ref_clk";
 444 +
 445 +               assigned-clocks = <&cs2000>;
 446 +               assigned-clock-rates = <24576000>; /* 1/1 divide */
 447 +       };
 448 +};
 449 +
 450 +&i2c3 {
 451 +       pinctrl-0 = <&i2c3_pins>;
 452 +       pinctrl-names = "default";
 453 +
 454 +       status = "okay";
 455 +
 456 +       clock-frequency = <400000>;
 457 +
 458 +       asm330lhh@6a {
 459 +               compatible = "st,asm330lhh";
 460 +               reg = <0x6a>;
 461 +
 462 +               interrupt-names = "int1", "int2";
 463 +               interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
 464 +                                     <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
 465 +               st,drdy-int-pin = <1>;
 466 +       };
 467 +};
 468 +
 469 +&i2c4 {
 470 +       status = "okay";
 471 +
 472 +       versaclock5: clock-generator@68 {
 473 +               compatible = "idt,9fgv0841";
 474 +               reg = <0x68>;
 475 +               #clock-cells = <1>;
 476 +               clocks = <&x23_clk>;
 477 +               clock-names = "xin";
 478 +       };
 479 +};
 480 +
 481 +&i2c5 {
 482 +       pinctrl-0 = <&i2c5_pins>;
 483 +       pinctrl-names = "default";
 484 +
 485 +       status = "okay";
 486 +
 487 +       clock-frequency = <100000>;
 488 +
 489 +       ak4613: codec@10 {
 490 +               compatible = "asahi-kasei,ak4613";
 491 +               #sound-dai-cells = <0>;
 492 +               reg = <0x10>;
 493 +               clocks = <&rcar_sound 3>;
 494 +
 495 +               asahi-kasei,in1-single-end;
 496 +               asahi-kasei,in2-single-end;
 497 +               asahi-kasei,out1-single-end;
 498 +               asahi-kasei,out2-single-end;
 499 +               asahi-kasei,out3-single-end;
 500 +               asahi-kasei,out4-single-end;
 501 +               asahi-kasei,out5-single-end;
 502 +               asahi-kasei,out6-single-end;
 503 +
 504 +               port {
 505 +                       ak4613_endpoint: endpoint {
 506 +                               remote-endpoint = <&rsnd_endpoint0>;
 507 +                       };
 508 +               };
 509 +       };
 510 +};
 511 +
 512 +&i2c_dvfs {
 513 +       status = "okay";
 514 +
 515 +       clock-frequency = <400000>;
 516 +
 517 +       pmic: pmic@30 {
 518 +               pinctrl-0 = <&irq0_pins>;
 519 +               pinctrl-names = "default";
 520 +
 521 +               compatible = "rohm,bd9571mwv";
 522 +               reg = <0x30>;
 523 +               interrupt-parent = <&intc_ex>;
 524 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 525 +               interrupt-controller;
 526 +               #interrupt-cells = <2>;
 527 +               gpio-controller;
 528 +               #gpio-cells = <2>;
 529 +               rohm,ddr-backup-power = <0xf>;
 530 +               rohm,rstbmode-level;
 531 +
 532 +               regulators {
 533 +                       dvfs: dvfs {
 534 +                               regulator-name = "dvfs";
 535 +                               regulator-min-microvolt = <750000>;
 536 +                               regulator-max-microvolt = <1030000>;
 537 +                               regulator-boot-on;
 538 +                               regulator-always-on;
 539 +                       };
 540 +               };
 541 +       };
 542 +
 543 +       eeprom@50 {
 544 +               compatible = "rohm,br24t01", "atmel,24c01";
 545 +               reg = <0x50>;
 546 +               pagesize = <8>;
 547 +       };
 548 +};
 549 +
 550 +&ohci0 {
 551 +       dr_mode = "otg";
 552 +       status = "okay";
 553 +};
 554 +
 555 +&ohci1 {
 556 +       status = "okay";
 557 +};
 558 +
 559 +&pcie_bus_clk {
 560 +       clock-frequency = <100000000>;
 561 +       status = "okay";
 562 +};
 563 +
 564 +&pciec0 {
 565 +       status = "okay";
 566 +};
 567 +
 568 +&pciec1 {
 569 +       status = "okay";
 570 +};
 571 +
 572 +&canfd {
 573 +       pinctrl-0 = <&canfd0_pins &canfd1_pins>;
 574 +       pinctrl-names = "default";
 575 +
 576 +       status = "okay";
 577 +
 578 +       channel0 {
 579 +               status = "okay";
 580 +       };
 581 +
 582 +       channel1 {
 583 +               status = "okay";
 584 +       };
 585 +};
 586 +
 587 +&pfc {
 588 +       pinctrl-0 = <&scif_clk_pins>;
 589 +       pinctrl-names = "default";
 590 +
 591 +       avb_pins: avb {
 592 +               mux {
 593 +                       groups = "avb_link", "avb_mdio", "avb_mii";
 594 +                       function = "avb";
 595 +               };
 596 +
 597 +               pins_mdio {
 598 +                       groups = "avb_mdio";
 599 +                       drive-strength = <24>;
 600 +               };
 601 +
 602 +               pins_mii_tx {
 603 +                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 604 +                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 605 +                       drive-strength = <12>;
 606 +               };
 607 +       };
 608 +
 609 +       hscif0_pins: hscif0 {
 610 +               groups = "hscif0_data", "hscif0_ctrl";
 611 +               function = "hscif0";
 612 +       };
 613 +
 614 +       hscif1_pins: hscif1 {
 615 +               groups = "hscif1_data_a";
 616 +               function = "hscif1";
 617 +       };
 618 +
 619 +       hscif2_pins: hscif2 {
 620 +               groups = "hscif2_data_c";
 621 +               function = "hscif2";
 622 +       };
 623 +
 624 +       i2c2_pins: i2c2 {
 625 +               groups = "i2c2_a";
 626 +               function = "i2c2";
 627 +       };
 628 +
 629 +       i2c3_pins: i2c3 {
 630 +               groups = "i2c3";
 631 +               function = "i2c3";
 632 +       };
 633 +
 634 +       i2c5_pins: i2c5 {
 635 +               groups = "i2c5";
 636 +               function = "i2c5";
 637 +       };
 638 +
 639 +       irq0_pins: irq0 {
 640 +               groups = "intc_ex_irq0";
 641 +               function = "intc_ex";
 642 +       };
 643 +
 644 +       scif1_pins: scif1 {
 645 +               groups = "scif1_data_b";
 646 +               function = "scif1";
 647 +       };
 648 +
 649 +       scif2_pins: scif2 {
 650 +               groups = "scif2_data_a";
 651 +               function = "scif2";
 652 +       };
 653 +
 654 +       scif5_pins: scif5 {
 655 +               groups = "scif5_data_a";
 656 +               function = "scif5";
 657 +       };
 658 +
 659 +       scif_clk_pins: scif_clk {
 660 +               groups = "scif_clk_a";
 661 +               function = "scif_clk";
 662 +       };
 663 +
 664 +       sdhi0_pins: sd0 {
 665 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 666 +               function = "sdhi0";
 667 +               power-source = <3300>;
 668 +       };
 669 +
 670 +       sdhi0_pins_uhs: sd0_uhs {
 671 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 672 +               function = "sdhi0";
 673 +               power-source = <1800>;
 674 +       };
 675 +
 676 +       sdhi2_pins: sd2 {
 677 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 678 +               function = "sdhi2";
 679 +               power-source = <3300>;
 680 +       };
 681 +
 682 +       sdhi2_pins_uhs: sd2_uhs {
 683 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 684 +               function = "sdhi2";
 685 +               power-source = <1800>;
 686 +       };
 687 +
 688 +       sdhi3_pins: sd3 {
 689 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 690 +               function = "sdhi3";
 691 +               power-source = <3300>;
 692 +       };
 693 +
 694 +       sdhi3_pins_uhs: sd3_uhs {
 695 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 696 +               function = "sdhi3";
 697 +               power-source = <1800>;
 698 +       };
 699 +
 700 +       sound_pins: sound {
 701 +               groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
 702 +               function = "ssi";
 703 +       };
 704 +
 705 +       sound_clk_pins: sound_clk {
 706 +               groups = "audio_clk_a_a", "audio_clk_b_a",
 707 +                        "audio_clkout_a", "audio_clkout3_b";
 708 +               function = "audio_clk";
 709 +       };
 710 +
 711 +       usb0_pins: usb0 {
 712 +               groups = "usb0";
 713 +               function = "usb0";
 714 +       };
 715 +
 716 +       usb1_pins: usb1 {
 717 +               groups = "usb1_ovc";
 718 +               function = "usb1";
 719 +       };
 720 +
 721 +       usb30_pins: usb30 {
 722 +               groups = "usb30", "usb30_ovc";
 723 +               function = "usb30";
 724 +       };
 725 +
 726 +       canfd0_pins: canfd0 {
 727 +               groups = "canfd0_data_a";
 728 +               function = "canfd0";
 729 +       };
 730 +
 731 +       canfd1_pins: canfd1 {
 732 +               groups = "canfd1_data";
 733 +               function = "canfd1";
 734 +       };
 735 +};
 736 +
 737 +&rcar_sound {
 738 +       pinctrl-0 = <&sound_pins &sound_clk_pins>;
 739 +       pinctrl-names = "default";
 740 +
 741 +       /* Single DAI */
 742 +       #sound-dai-cells = <0>;
 743 +
 744 +       /* audio_clkout0/1/2/3 */
 745 +       #clock-cells = <1>;
 746 +       clock-frequency = <12288000 11289600>;
 747 +
 748 +       status = "okay";
 749 +
 750 +       /* update <audio_clk_b> to <cs2000> */
 751 +       clocks = <&cpg CPG_MOD 1005>,
 752 +                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 753 +                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 754 +                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 755 +                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 756 +                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 757 +                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 758 +                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 759 +                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 760 +                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 761 +                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 762 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 763 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 764 +                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 765 +                <&audio_clk_a>, <&cs2000>,
 766 +                <&audio_clk_c>,
 767 +                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
 768 +
 769 +       ports {
 770 +               #address-cells = <1>;
 771 +               #size-cells = <0>;
 772 +               rsnd_port0: port@0 {
 773 +                       reg = <0>;
 774 +                       rsnd_endpoint0: endpoint {
 775 +                               remote-endpoint = <&ak4613_endpoint>;
 776 +
 777 +                               dai-format = "left_j";
 778 +                               bitclock-master = <&rsnd_endpoint0>;
 779 +                               frame-master = <&rsnd_endpoint0>;
 780 +
 781 +                               playback = <&ssi3>; //ssi0 -> ssi3
 782 +                               capture  = <&ssi4>; //ssi1 -> ssi4
 783 +                       };
 784 +               };
 785 +       };
 786 +};
 787 +
 788 +&rwdt {
 789 +       timeout-sec = <60>;
 790 +       status = "okay";
 791 +};
 792 +
 793 +&scif1 {
 794 +       pinctrl-0 = <&scif1_pins>;
 795 +       pinctrl-names = "default";
 796 +
 797 +       uart-has-rtscts;
 798 +       /* Please use exclusively to the hscif1 node */
 799 +       status = "okay";
 800 +};
 801 +
 802 +&scif2 {
 803 +       pinctrl-0 = <&scif2_pins>;
 804 +       pinctrl-names = "default";
 805 +
 806 +       status = "okay";
 807 +};
 808 +
 809 +&scif5 {
 810 +       pinctrl-0 = <&scif5_pins>;
 811 +       pinctrl-names = "default";
 812 +
 813 +       status = "okay";
 814 +};
 815 +
 816 +&scif_clk {
 817 +       clock-frequency = <14745600>;
 818 +};
 819 +
 820 +&sdhi0 {
 821 +       pinctrl-0 = <&sdhi0_pins>;
 822 +       pinctrl-1 = <&sdhi0_pins_uhs>;
 823 +       pinctrl-names = "default", "state_uhs";
 824 +
 825 +       vmmc-supply = <&vcc_sdhi0>;
 826 +       vqmmc-supply = <&vccq_sdhi0>;
 827 +       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 828 +       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 829 +       bus-width = <4>;
 830 +       sd-uhs-sdr50;
 831 +       sd-uhs-sdr104;
 832 +       status = "okay";
 833 +};
 834 +
 835 +&sdhi2 {
 836 +       /* used for on-board 8bit eMMC */
 837 +       pinctrl-0 = <&sdhi2_pins>;
 838 +       pinctrl-1 = <&sdhi2_pins_uhs>;
 839 +       pinctrl-names = "default", "state_uhs";
 840 +
 841 +       iommus = <&ipmmu_ds1 34>;
 842 +
 843 +       vmmc-supply = <&reg_3p3v>;
 844 +       vqmmc-supply = <&reg_1p8v>;
 845 +       bus-width = <8>;
 846 +       mmc-hs200-1_8v;
 847 +       mmc-hs400-1_8v;
 848 +       no-sd;
 849 +       no-sdio;
 850 +       non-removable;
 851 +       fixed-emmc-driver-type = <1>;
 852 +       status = "okay";
 853 +};
 854 +
 855 +&sdhi3 {
 856 +       pinctrl-0 = <&sdhi3_pins>;
 857 +       pinctrl-1 = <&sdhi3_pins_uhs>;
 858 +       pinctrl-names = "default", "state_uhs";
 859 +
 860 +       vmmc-supply = <&vcc_sdhi3>;
 861 +       vqmmc-supply = <&vccq_sdhi3>;
 862 +       cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 863 +       wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 864 +       bus-width = <4>;
 865 +       sd-uhs-sdr50;
 866 +       sd-uhs-sdr104;
 867 +       status = "okay";
 868 +};
 869 +
 870 +&ssi4 {
 871 +       shared-pin;
 872 +};
 873 +
 874 +&usb_extal_clk {
 875 +       clock-frequency = <50000000>;
 876 +};
 877 +
 878 +&usb2_phy0 {
 879 +       pinctrl-0 = <&usb0_pins>;
 880 +       pinctrl-names = "default";
 881 +
 882 +       status = "okay";
 883 +};
 884 +
 885 +&usb2_phy1 {
 886 +       pinctrl-0 = <&usb1_pins>;
 887 +       pinctrl-names = "default";
 888 +
 889 +       status = "okay";
 890 +};
 891 +
 892 +&usb3_peri0 {
 893 +       phys = <&usb3_phy0>;
 894 +       phy-names = "usb";
 895 +
 896 +       status = "okay";
 897 +};
 898 +
 899 +&usb3_phy0 {
 900 +       status = "okay";
 901 +};
 902 +
 903 +&usb3s0_clk {
 904 +       clock-frequency = <100000000>;
 905 +};
 906 +
 907 +&vin0 {
 908 +       status = "okay";
 909 +};
 910 +
 911 +&vin1 {
 912 +       status = "okay";
 913 +};
 914 +
 915 +&vin2 {
 916 +       status = "okay";
 917 +};
 918 +
 919 +&vin3 {
 920 +       status = "okay";
 921 +};
 922 +
 923 +&vin4 {
 924 +       status = "okay";
 925 +};
 926 +
 927 +&vin5 {
 928 +       status = "okay";
 929 +};
 930 +
 931 +&vin6 {
 932 +       status = "okay";
 933 +};
 934 +
 935 +&vin7 {
 936 +       status = "okay";
 937 +};
 938 +
 939 +&xhci0 {
 940 +       pinctrl-0 = <&usb30_pins>;
 941 +       pinctrl-names = "default";
 942 +
 943 +       status = "okay";
 944 +};
 945 diff --git a/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
 946 new file mode 100644
 947 index 000000000000..3d1107f6d9cc
 948 --- /dev/null
 949 +++ b/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
 950 @@ -0,0 +1,392 @@
 951 +/*
 952 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
 953 + *
 954 + * Copyright (C) 2019 Panasonic Corp.
 955 + * Copyright (C) 2020 Konsulko Group
 956 + *
 957 + * This file is licensed under the terms of the GNU General Public License
 958 + * version 2.  This program is licensed "as is" without any warranty of any
 959 + * kind, whether express or implied.
 960 + */
 961 +
 962 +/*
 963 + * This file is for the most part derived from:
 964 + *
 965 + * - r8a77951-salvator-xs-4x2g.dts
 966 + * - r8a77951-salvator-xs.dts
 967 + * - salvator-xs.dtsi
 968 + *
 969 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
 970 + */
 971 +
 972 +/dts-v1/;
 973 +#include "r8a77951.dtsi"
 974 +#include "agl-refhw-common.dtsi"
 975 +
 976 +/ {
 977 +       model = "AGL Reference Hardware based on r8a77951 ES3.0+ with 8GiB (4 x 2 GiB)";
 978 +       compatible = "agl,refhw-h3", "renesas,r8a7795";
 979 +
 980 +       memory@48000000 {
 981 +               device_type = "memory";
 982 +               /* first 128MB is reserved for secure area. */
 983 +               reg = <0x0 0x48000000 0x0 0x78000000>;
 984 +       };
 985 +
 986 +       memory@500000000 {
 987 +               device_type = "memory";
 988 +               reg = <0x5 0x00000000 0x0 0x80000000>;
 989 +       };
 990 +
 991 +       memory@600000000 {
 992 +               device_type = "memory";
 993 +               reg = <0x6 0x00000000 0x0 0x80000000>;
 994 +       };
 995 +
 996 +       memory@700000000 {
 997 +               device_type = "memory";
 998 +               reg = <0x7 0x00000000 0x0 0x80000000>;
 999 +       };
1000 +
1001 +       reserved-memory {
1002 +               #address-cells = <2>;
1003 +               #size-cells = <2>;
1004 +               ranges;
1005 +
1006 +               /* device specific region for Lossy Decompression */
1007 +               lossy_decompress: linux,lossy_decompress@54000000 {
1008 +                       no-map;
1009 +                       reg = <0x00000000 0x54000000 0x0 0x03000000>;
1010 +               };
1011 +
1012 +               /* For Audio DSP */
1013 +               adsp_reserved: linux,adsp@57000000 {
1014 +                       compatible = "shared-dma-pool";
1015 +                       reusable;
1016 +                       reg = <0x00000000 0x57000000 0x0 0x01000000>;
1017 +               };
1018 +
1019 +               /* global autoconfigured region for contiguous allocations */
1020 +               linux,cma@58000000 {
1021 +                       compatible = "shared-dma-pool";
1022 +                       reusable;
1023 +                       reg = <0x00000000 0x58000000 0x0 0x18000000>;
1024 +                       linux,cma-default;
1025 +               };
1026 +
1027 +               /* device specific region for contiguous allocations */
1028 +               mmp_reserved: linux,multimedia@70000000 {
1029 +                       compatible = "shared-dma-pool";
1030 +                       reusable;
1031 +                       reg = <0x00000000 0x70000000 0x0 0x10000000>;
1032 +               };
1033 +       };
1034 +
1035 +       mmngr {
1036 +               compatible = "renesas,mmngr";
1037 +               memory-region = <&mmp_reserved>, <&lossy_decompress>;
1038 +       };
1039 +
1040 +       mmngrbuf {
1041 +               compatible = "renesas,mmngrbuf";
1042 +       };
1043 +
1044 +       vspm_if {
1045 +               compatible = "renesas,vspm_if";
1046 +       };
1047 +
1048 +       vga {
1049 +               port {
1050 +                       vga_in: endpoint {
1051 +                               /delete-property/remote-endpoint;
1052 +                       };
1053 +               };
1054 +       };
1055 +
1056 +       vga-encoder {
1057 +               ports {
1058 +                       port@0 {
1059 +                               adv7123_in: endpoint {
1060 +                                       /delete-property/remote-endpoint;
1061 +                               };
1062 +                       };
1063 +
1064 +                       port@1 {
1065 +                               adv7123_out: endpoint {
1066 +                                       /delete-property/remote-endpoint;
1067 +                               };
1068 +                       };
1069 +               };
1070 +       };
1071 +
1072 +};
1073 +
1074 +&adsp {
1075 +       status = "okay";
1076 +       memory-region = <&adsp_reserved>;
1077 +};
1078 +
1079 +&du {
1080 +       clocks = <&cpg CPG_MOD 724>,
1081 +                <&cpg CPG_MOD 723>,
1082 +                <&cpg CPG_MOD 722>,
1083 +                <&cpg CPG_MOD 721>,
1084 +                <&versaclock6 1>,
1085 +                <&x21_clk>,
1086 +                <&x22_clk>,
1087 +                <&versaclock6 2>;
1088 +       clock-names = "du.0", "du.1", "du.2", "du.3",
1089 +                     "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1090 +};
1091 +
1092 +&ehci2 {
1093 +       status = "okay";
1094 +};
1095 +
1096 +&ehci3 {
1097 +       dr_mode = "otg";
1098 +       status = "okay";
1099 +};
1100 +
1101 +&hsusb3 {
1102 +       dr_mode = "otg";
1103 +       status = "okay";
1104 +};
1105 +
1106 +&sound_card {
1107 +       dais = <&rsnd_port0     /* ak4613 */
1108 +               &rsnd_port1     /* HDMI0  */
1109 +               &rsnd_port2>;   /* HDMI1  */
1110 +};
1111 +
1112 +&hdmi0 {
1113 +       status = "okay";
1114 +
1115 +       ports {
1116 +               port@1 {
1117 +                       reg = <1>;
1118 +                       rcar_dw_hdmi0_out: endpoint {
1119 +                               remote-endpoint = <&hdmi0_con>;
1120 +                       };
1121 +               };
1122 +               port@2 {
1123 +                       reg = <2>;
1124 +                       dw_hdmi0_snd_in: endpoint {
1125 +                               remote-endpoint = <&rsnd_endpoint1>;
1126 +                       };
1127 +               };
1128 +       };
1129 +};
1130 +
1131 +&hdmi0_con {
1132 +       remote-endpoint = <&rcar_dw_hdmi0_out>;
1133 +};
1134 +
1135 +&hdmi1 {
1136 +       status = "okay";
1137 +
1138 +       ports {
1139 +               port@1 {
1140 +                       reg = <1>;
1141 +                       rcar_dw_hdmi1_out: endpoint {
1142 +                               remote-endpoint = <&hdmi1_con>;
1143 +                       };
1144 +               };
1145 +               port@2 {
1146 +                       reg = <2>;
1147 +                       dw_hdmi1_snd_in: endpoint {
1148 +                               remote-endpoint = <&rsnd_endpoint2>;
1149 +                       };
1150 +               };
1151 +       };
1152 +};
1153 +
1154 +&hdmi1_con {
1155 +       remote-endpoint = <&rcar_dw_hdmi1_out>;
1156 +};
1157 +
1158 +&ohci2 {
1159 +       status = "okay";
1160 +};
1161 +
1162 +&ohci3 {
1163 +       dr_mode = "otg";
1164 +       status = "okay";
1165 +};
1166 +
1167 +&rcar_sound {
1168 +       ports {
1169 +               /* rsnd_port0 is on salvator-common */
1170 +               rsnd_port1: port@1 {
1171 +                       reg = <1>;
1172 +                       rsnd_endpoint1: endpoint {
1173 +                               remote-endpoint = <&dw_hdmi0_snd_in>;
1174 +
1175 +                               dai-format = "i2s";
1176 +                               bitclock-master = <&rsnd_endpoint1>;
1177 +                               frame-master = <&rsnd_endpoint1>;
1178 +
1179 +                               playback = <&ssi2>;
1180 +                       };
1181 +               };
1182 +               rsnd_port2: port@2 {
1183 +                       reg = <2>;
1184 +                       rsnd_endpoint2: endpoint {
1185 +                               remote-endpoint = <&dw_hdmi1_snd_in>;
1186 +
1187 +                               dai-format = "i2s";
1188 +                               bitclock-master = <&rsnd_endpoint2>;
1189 +                               frame-master = <&rsnd_endpoint2>;
1190 +
1191 +                               playback = <&ssi3>;
1192 +                       };
1193 +               };
1194 +       };
1195 +};
1196 +
1197 +&pfc {
1198 +       usb2_pins: usb2 {
1199 +               groups = "usb2", "usb2_ovc";
1200 +               function = "usb2";
1201 +       };
1202 +
1203 +       /*
1204 +        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1205 +        *   (when SW31 is the default setting on Salvator-XS).
1206 +        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1207 +        *   r8a77951 with Salvator-XS.
1208 +        *   Hence the SW31 setting must be changed like 2) below.
1209 +        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1210 +        *      - Connect GP6_3[01] to ADV7842.
1211 +        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1212 +        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1213 +        *      - Connect GP6_{04,21} to ADV7842.
1214 +        */
1215 +       usb2_ch3_pins: usb2_ch3 {
1216 +               groups = "usb2_ch3";
1217 +               function = "usb2_ch3";
1218 +       };
1219 +};
1220 +
1221 +&usb2_phy2 {
1222 +       pinctrl-0 = <&usb2_pins>;
1223 +       pinctrl-names = "default";
1224 +
1225 +       status = "okay";
1226 +};
1227 +
1228 +&usb2_phy3 {
1229 +       pinctrl-0 = <&usb2_ch3_pins>;
1230 +       pinctrl-names = "default";
1231 +
1232 +       status = "okay";
1233 +};
1234 +
1235 +&vspbc {
1236 +       status = "okay";
1237 +};
1238 +
1239 +&vspbd {
1240 +       status = "okay";
1241 +};
1242 +
1243 +&vspi0 {
1244 +       status = "okay";
1245 +};
1246 +
1247 +&vspi1 {
1248 +       status = "okay";
1249 +};
1250 +
1251 +/* End r8a77951-salvator-xs.dts content */
1252 +
1253 +
1254 +/* Start r8a77951-salvator-xs-4x2g.dts content */
1255 +
1256 +&pciec0 {
1257 +       /* Map all possible DDR as inbound ranges */
1258 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1259 +};
1260 +
1261 +&pciec1 {
1262 +       /* Map all possible DDR as inbound ranges */
1263 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1264 +};
1265 +
1266 +/* End r8a77951-salvator-xs-4x2g.dts content */
1267 +
1268 +
1269 +/* Start salvator-xs.dts content */
1270 +
1271 +&extal_clk {
1272 +       clock-frequency = <16640000>;
1273 +};
1274 +
1275 +&i2c4 {
1276 +       clock-frequency = <400000>;
1277 +
1278 +       versaclock6: clock-generator@6a {
1279 +               compatible = "idt,5p49v6901";
1280 +               reg = <0x6a>;
1281 +               #clock-cells = <1>;
1282 +               clocks = <&x23_clk>;
1283 +               clock-names = "xin";
1284 +       };
1285 +};
1286 +
1287 +/* End salvator-xs.dts content */
1288 +
1289 +
1290 +/* Start reference hardware specific tweaks */
1291 +
1292 +&du {
1293 +       ports {
1294 +               port@0 {
1295 +                       endpoint {
1296 +                               /delete-property/remote-endpoint;
1297 +                       };
1298 +               };
1299 +
1300 +               port@3 {
1301 +                       endpoint {
1302 +                               /delete-property/remote-endpoint;
1303 +                       };
1304 +               };
1305 +       };
1306 +};
1307 +
1308 +&lvds0 {
1309 +       status = "disabled";
1310 +};
1311 +
1312 +&pwm1 {
1313 +       status = "disabled";
1314 +};
1315 +
1316 +&scif_clk {
1317 +       clock-frequency = <0>;
1318 +};
1319 +
1320 +&sdhi0 {
1321 +       /delete-property/ wp-gpios;
1322 +       non-removable;
1323 +};
1324 +
1325 +&sdhi3 {
1326 +       /delete-property/ wp-gpios;
1327 +       non-removable;
1328 +};
1329 +
1330 +&gpio6 {
1331 +       /* Enable the CAN 1 & 2 transceivers */
1332 +       can-1-transceiver-stb {
1333 +               gpio-hog;
1334 +               gpios = <21 GPIO_ACTIVE_HIGH>;
1335 +               output-low;
1336 +       };
1337 +       can-2-transceiver-stb {
1338 +               gpio-hog;
1339 +               gpios = <12 GPIO_ACTIVE_HIGH>;
1340 +               output-low;
1341 +       };
1342 +};
1343 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1344 index fe156e8f88b8..da295b106561 100644
1345 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1346 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1347 @@ -97,6 +97,21 @@ static const struct adv748x_register_map adv748x_default_addresses[] = {
1348         [ADV748X_PAGE_TXA] = { "txa", 0x4a },
1349  };
1350
1351 +static const struct adv748x_register_map adv748x_default_addresses2[] = {
1352 +       [ADV748X_PAGE_IO] = { "main", 0x71 },
1353 +       [ADV748X_PAGE_DPLL] = { "dpll", 0x27 },
1354 +       [ADV748X_PAGE_CP] = { "cp", 0x23 },
1355 +       [ADV748X_PAGE_HDMI] = { "hdmi", 0x35 },
1356 +       [ADV748X_PAGE_EDID] = { "edid", 0x37 },
1357 +       [ADV748X_PAGE_REPEATER] = { "repeater", 0x33 },
1358 +       [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x28 },
1359 +       [ADV748X_PAGE_CBUS] = { "cbus", 0x29 },
1360 +       [ADV748X_PAGE_CEC] = { "cec", 0x42 },
1361 +       [ADV748X_PAGE_SDP] = { "sdp", 0x78 },
1362 +       [ADV748X_PAGE_TXB] = { "txb", 0x49 },
1363 +       [ADV748X_PAGE_TXA] = { "txa", 0x4b },
1364 +};
1365 +
1366  static int adv748x_read_check(struct adv748x_state *state,
1367                               int client_page, u8 reg)
1368  {
1369 @@ -183,10 +198,17 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
1370         int ret;
1371
1372         for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1373 -               state->i2c_clients[i] = i2c_new_ancillary_device(
1374 +               if ((state->client->addr << 1) == 0xe0) {
1375 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1376                                 state->client,
1377                                 adv748x_default_addresses[i].name,
1378                                 adv748x_default_addresses[i].default_addr);
1379 +               } else {
1380 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1381 +                               state->client,
1382 +                               adv748x_default_addresses2[i].name,
1383 +                               adv748x_default_addresses2[i].default_addr);
1384 +               }
1385
1386                 if (IS_ERR(state->i2c_clients[i])) {
1387                         adv_err(state, "failed to create i2c client %u\n", i);
1388 --
1389 2.31.1
1390