1 From e8df6330789b106821b9bb59177efa8a191adfda Mon Sep 17 00:00:00 2001
2 From: Scott Murray <scott.murray@konsulko.com>
3 Date: Tue, 21 Sep 2021 15:45:18 -0400
4 Subject: [PATCH 2/4] Add AGL reference hardware support
6 Upstream-Status: pending
8 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
9 Signed-off-by: Raquel Medina <raquel.medina@konsulko.com>
10 [asm330lhh interrupt fix]
11 Signed-off-by: Hiroyuki Ishii <ishii.hiroyuki002@jp.panasonic.com>
13 .../boot/dts/renesas/agl-refhw-common.dtsi | 922 ++++++++++++++++++
14 .../boot/dts/renesas/r8a77951-agl-refhw.dts | 392 ++++++++
15 drivers/media/i2c/adv748x/adv748x-core.c | 24 +-
16 3 files changed, 1337 insertions(+), 1 deletion(-)
17 create mode 100644 arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
18 create mode 100644 arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
20 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
22 index 000000000000..3f6f8d86f76d
24 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
26 +// SPDX-License-Identifier: GPL-2.0
28 + * Device Tree Source for common parts of AGL Reference Hardware board variants
30 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
31 + * Copyright (C) 2020 Konsulko Group
35 + * This file is derived from salvator-common.dtsi
37 + * It is currently unclear if the modifications made are such that they could
38 + * be done on top of salvator-common.dtsi to allow removing the duplication.
39 + * It is likely that the common pieces with salvator-common.dtsi would need to
40 + * be factored out into a new common file, which is perhaps hard to justify.
46 + * This command is required when Playback/Capture
48 + * amixer set "DVC Out" 100%
49 + * amixer set "DVC In" 100%
53 + * amixer set "DVC Out Mute" on
54 + * amixer set "DVC In Mute" on
56 + * You can use Volume Ramp
58 + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
59 + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
60 + * amixer set "DVC Out Ramp" on
62 + * amixer set "DVC Out" 80% // Volume Down
63 + * amixer set "DVC Out" 100% // Volume Up
66 +#include <dt-bindings/gpio/gpio.h>
83 + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
84 + stdout-path = "serial0:115200n8";
87 + audio_clkout: audio-clkout {
89 + * This is same as <&rcar_sound 0>
90 + * but needed to avoid cs2000/rcar_sound probe dead-lock
92 + compatible = "fixed-clock";
94 + clock-frequency = <12288000>;
98 + compatible = "renesas,avb-mch-gen3";
99 + reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
100 + reg-name = "adg_avb";
102 + clocks = <&cpg CPG_MOD 922>;
103 + clock-names = "adg";
104 + resets = <&cpg 922>;
108 + compatible = "hdmi-connector";
109 + label = "HDMI0 IN";
113 + hdmi_in_con: endpoint {
114 + remote-endpoint = <&adv7481_hdmi>;
120 + compatible = "hdmi-connector";
121 + label = "HDMI2 IN";
125 + hdmi_in_con2: endpoint {
126 + remote-endpoint = <&adv7481_hdmi2>;
131 + reg_1p8v: regulator0 {
132 + compatible = "regulator-fixed";
133 + regulator-name = "fixed-1.8V";
134 + regulator-min-microvolt = <1800000>;
135 + regulator-max-microvolt = <1800000>;
137 + regulator-always-on;
140 + reg_3p3v: regulator1 {
141 + compatible = "regulator-fixed";
142 + regulator-name = "fixed-3.3V";
143 + regulator-min-microvolt = <3300000>;
144 + regulator-max-microvolt = <3300000>;
146 + regulator-always-on;
149 + reg_12v: regulator2 {
150 + compatible = "regulator-fixed";
151 + regulator-name = "fixed-12V";
152 + regulator-min-microvolt = <12000000>;
153 + regulator-max-microvolt = <12000000>;
155 + regulator-always-on;
158 + sound_card: sound {
159 + compatible = "audio-graph-card";
163 + dais = <&rsnd_port0>;
166 + vcc_sdhi0: regulator-vcc-sdhi0 {
167 + compatible = "regulator-fixed";
169 + regulator-name = "SDHI0 Vcc";
170 + regulator-min-microvolt = <3300000>;
171 + regulator-max-microvolt = <3300000>;
173 + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
174 + enable-active-high;
177 + vccq_sdhi0: regulator-vccq-sdhi0 {
178 + compatible = "regulator-gpio";
180 + regulator-name = "SDHI0 VccQ";
181 + regulator-min-microvolt = <1800000>;
182 + regulator-max-microvolt = <3300000>;
184 + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
185 + gpios-states = <1>;
186 + states = <3300000 1
190 + vcc_sdhi3: regulator-vcc-sdhi3 {
191 + compatible = "regulator-fixed";
193 + regulator-name = "SDHI3 Vcc";
194 + regulator-min-microvolt = <3300000>;
195 + regulator-max-microvolt = <3300000>;
197 + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
198 + enable-active-high;
201 + vccq_sdhi3: regulator-vccq-sdhi3 {
202 + compatible = "regulator-gpio";
204 + regulator-name = "SDHI3 VccQ";
205 + regulator-min-microvolt = <1800000>;
206 + regulator-max-microvolt = <3300000>;
208 + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
209 + gpios-states = <1>;
210 + states = <3300000 1
215 + compatible = "hdmi-connector";
216 + label = "HDMI0 OUT";
220 + hdmi0_con: endpoint {
226 + compatible = "hdmi-connector";
227 + label = "HDMI1 OUT";
231 + hdmi1_con: endpoint {
237 + compatible = "fixed-clock";
238 + #clock-cells = <0>;
239 + clock-frequency = <24576000>;
242 + /* External DU dot clocks */
243 + x21_clk: x21-clock {
244 + compatible = "fixed-clock";
245 + #clock-cells = <0>;
246 + clock-frequency = <33000000>;
249 + x22_clk: x22-clock {
250 + compatible = "fixed-clock";
251 + #clock-cells = <0>;
252 + clock-frequency = <33000000>;
255 + x23_clk: x23-clock {
256 + compatible = "fixed-clock";
257 + #clock-cells = <0>;
258 + clock-frequency = <25000000>;
263 + cpu-supply = <&dvfs>;
267 + clock-frequency = <22579200>;
271 + pinctrl-0 = <&avb_pins>;
272 + pinctrl-names = "default";
273 + phy-handle = <&phy0>;
274 + phy-mode = "rgmii-txid";
277 + phy0: ethernet-phy@0 {
278 + rxc-skew-ps = <1500>;
280 + interrupt-parent = <&gpio2>;
281 + interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
282 + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
293 + csi40_in: endpoint {
295 + data-lanes = <1 2 3 4>;
296 + remote-endpoint = <&adv7481_txa>;
309 + csi41_in: endpoint {
311 + data-lanes = <1 2 3 4>;
312 + remote-endpoint = <&adv7481_txa2>;
333 + clock-frequency = <32768>;
337 + pinctrl-0 = <&hscif0_pins>;
338 + pinctrl-names = "default";
345 + pinctrl-0 = <&hscif1_pins>;
346 + pinctrl-names = "default";
348 + /* Please use exclusively to the scif1 node */
353 + pinctrl-0 = <&hscif2_pins>;
354 + pinctrl-names = "default";
365 + pinctrl-0 = <&i2c2_pins>;
366 + pinctrl-names = "default";
370 + clock-frequency = <100000>;
372 + video-receiver@70 {
373 + compatible = "adi,adv7481";
374 + reg = <0x70 0x26 0x22 0x34 0x36 0x32
375 + 0x31 0x30 0x41 0x79 0x4a 0x48>;
376 + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
377 + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
379 + #address-cells = <1>;
382 + interrupt-parent = <&gpio0>;
383 + interrupt-names = "intrq1", "intrq3";
384 + interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
385 + <5 IRQ_TYPE_LEVEL_LOW>;
390 + adv7481_hdmi: endpoint {
391 + remote-endpoint = <&hdmi_in_con>;
398 + adv7481_txa: endpoint {
400 + data-lanes = <1 2 3 4>;
401 + remote-endpoint = <&csi40_in>;
407 + video-receiver@71 {
408 + compatible = "adi,adv7481";
409 + reg = <0x71 0x27 0x23 0x35 0x37 0x33
410 + 0x28 0x29 0x42 0x78 0x4b 0x49>;
411 + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
412 + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
414 + #address-cells = <1>;
417 + interrupt-parent = <&gpio6>;
418 + interrupt-names = "intrq1", "intrq3";
419 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
420 + <1 IRQ_TYPE_LEVEL_LOW>;
425 + adv7481_hdmi2: endpoint {
426 + remote-endpoint = <&hdmi_in_con2>;
433 + adv7481_txa2: endpoint {
435 + data-lanes = <1 2 3 4>;
436 + remote-endpoint = <&csi41_in>;
441 + cs2000: clk_multiplier@4f {
442 + #clock-cells = <0>;
443 + compatible = "cirrus,cs2000-cp";
445 + clocks = <&audio_clkout>, <&x12_clk>;
446 + clock-names = "clk_in", "ref_clk";
448 + assigned-clocks = <&cs2000>;
449 + assigned-clock-rates = <24576000>; /* 1/1 divide */
454 + pinctrl-0 = <&i2c3_pins>;
455 + pinctrl-names = "default";
459 + clock-frequency = <400000>;
462 + compatible = "st,asm330lhh";
465 + interrupt-names = "int1", "int2";
466 + interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
467 + <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
468 + st,drdy-int-pin = <1>;
475 + versaclock5: clock-generator@68 {
476 + compatible = "idt,9fgv0841";
478 + #clock-cells = <1>;
479 + clocks = <&x23_clk>;
480 + clock-names = "xin";
485 + pinctrl-0 = <&i2c5_pins>;
486 + pinctrl-names = "default";
490 + clock-frequency = <100000>;
493 + compatible = "asahi-kasei,ak4613";
494 + #sound-dai-cells = <0>;
496 + clocks = <&rcar_sound 3>;
498 + asahi-kasei,in1-single-end;
499 + asahi-kasei,in2-single-end;
500 + asahi-kasei,out1-single-end;
501 + asahi-kasei,out2-single-end;
502 + asahi-kasei,out3-single-end;
503 + asahi-kasei,out4-single-end;
504 + asahi-kasei,out5-single-end;
505 + asahi-kasei,out6-single-end;
508 + ak4613_endpoint: endpoint {
509 + remote-endpoint = <&rsnd_endpoint0>;
518 + clock-frequency = <400000>;
521 + pinctrl-0 = <&irq0_pins>;
522 + pinctrl-names = "default";
524 + compatible = "rohm,bd9571mwv";
526 + interrupt-parent = <&intc_ex>;
527 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
528 + interrupt-controller;
529 + #interrupt-cells = <2>;
532 + rohm,ddr-backup-power = <0xf>;
533 + rohm,rstbmode-level;
537 + regulator-name = "dvfs";
538 + regulator-min-microvolt = <750000>;
539 + regulator-max-microvolt = <1030000>;
541 + regulator-always-on;
547 + compatible = "rohm,br24t01", "atmel,24c01";
563 + clock-frequency = <100000000>;
576 + pinctrl-0 = <&canfd0_pins &canfd1_pins>;
577 + pinctrl-names = "default";
591 + pinctrl-0 = <&scif_clk_pins>;
592 + pinctrl-names = "default";
596 + groups = "avb_link", "avb_mdio", "avb_mii";
601 + groups = "avb_mdio";
602 + drive-strength = <24>;
606 + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
607 + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
608 + drive-strength = <12>;
612 + hscif0_pins: hscif0 {
613 + groups = "hscif0_data", "hscif0_ctrl";
614 + function = "hscif0";
617 + hscif1_pins: hscif1 {
618 + groups = "hscif1_data_a";
619 + function = "hscif1";
622 + hscif2_pins: hscif2 {
623 + groups = "hscif2_data_c";
624 + function = "hscif2";
643 + groups = "intc_ex_irq0";
644 + function = "intc_ex";
647 + scif1_pins: scif1 {
648 + groups = "scif1_data_b";
649 + function = "scif1";
652 + scif2_pins: scif2 {
653 + groups = "scif2_data_a";
654 + function = "scif2";
657 + scif5_pins: scif5 {
658 + groups = "scif5_data_a";
659 + function = "scif5";
662 + scif_clk_pins: scif_clk {
663 + groups = "scif_clk_a";
664 + function = "scif_clk";
668 + groups = "sdhi0_data4", "sdhi0_ctrl";
669 + function = "sdhi0";
670 + power-source = <3300>;
673 + sdhi0_pins_uhs: sd0_uhs {
674 + groups = "sdhi0_data4", "sdhi0_ctrl";
675 + function = "sdhi0";
676 + power-source = <1800>;
680 + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
681 + function = "sdhi2";
682 + power-source = <3300>;
685 + sdhi2_pins_uhs: sd2_uhs {
686 + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
687 + function = "sdhi2";
688 + power-source = <1800>;
692 + groups = "sdhi3_data4", "sdhi3_ctrl";
693 + function = "sdhi3";
694 + power-source = <3300>;
697 + sdhi3_pins_uhs: sd3_uhs {
698 + groups = "sdhi3_data4", "sdhi3_ctrl";
699 + function = "sdhi3";
700 + power-source = <1800>;
703 + sound_pins: sound {
704 + groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
708 + sound_clk_pins: sound_clk {
709 + groups = "audio_clk_a_a", "audio_clk_b_a",
710 + "audio_clkout_a", "audio_clkout3_b";
711 + function = "audio_clk";
720 + groups = "usb1_ovc";
724 + usb30_pins: usb30 {
725 + groups = "usb30", "usb30_ovc";
726 + function = "usb30";
729 + canfd0_pins: canfd0 {
730 + groups = "canfd0_data_a";
731 + function = "canfd0";
734 + canfd1_pins: canfd1 {
735 + groups = "canfd1_data";
736 + function = "canfd1";
741 + pinctrl-0 = <&sound_pins &sound_clk_pins>;
742 + pinctrl-names = "default";
745 + #sound-dai-cells = <0>;
747 + /* audio_clkout0/1/2/3 */
748 + #clock-cells = <1>;
749 + clock-frequency = <12288000 11289600>;
753 + /* update <audio_clk_b> to <cs2000> */
754 + clocks = <&cpg CPG_MOD 1005>,
755 + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
756 + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
757 + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
758 + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
759 + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
760 + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
761 + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
762 + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
763 + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
764 + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
765 + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
766 + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
767 + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
768 + <&audio_clk_a>, <&cs2000>,
770 + <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
773 + #address-cells = <1>;
775 + rsnd_port0: port@0 {
777 + rsnd_endpoint0: endpoint {
778 + remote-endpoint = <&ak4613_endpoint>;
780 + dai-format = "left_j";
781 + bitclock-master = <&rsnd_endpoint0>;
782 + frame-master = <&rsnd_endpoint0>;
784 + playback = <&ssi3>; //ssi0 -> ssi3
785 + capture = <&ssi4>; //ssi1 -> ssi4
792 + timeout-sec = <60>;
797 + pinctrl-0 = <&scif1_pins>;
798 + pinctrl-names = "default";
801 + /* Please use exclusively to the hscif1 node */
806 + pinctrl-0 = <&scif2_pins>;
807 + pinctrl-names = "default";
813 + pinctrl-0 = <&scif5_pins>;
814 + pinctrl-names = "default";
820 + clock-frequency = <14745600>;
824 + pinctrl-0 = <&sdhi0_pins>;
825 + pinctrl-1 = <&sdhi0_pins_uhs>;
826 + pinctrl-names = "default", "state_uhs";
828 + vmmc-supply = <&vcc_sdhi0>;
829 + vqmmc-supply = <&vccq_sdhi0>;
830 + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
831 + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
839 + /* used for on-board 8bit eMMC */
840 + pinctrl-0 = <&sdhi2_pins>;
841 + pinctrl-1 = <&sdhi2_pins_uhs>;
842 + pinctrl-names = "default", "state_uhs";
844 + iommus = <&ipmmu_ds1 34>;
846 + vmmc-supply = <®_3p3v>;
847 + vqmmc-supply = <®_1p8v>;
854 + fixed-emmc-driver-type = <1>;
859 + pinctrl-0 = <&sdhi3_pins>;
860 + pinctrl-1 = <&sdhi3_pins_uhs>;
861 + pinctrl-names = "default", "state_uhs";
863 + vmmc-supply = <&vcc_sdhi3>;
864 + vqmmc-supply = <&vccq_sdhi3>;
865 + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
866 + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
878 + clock-frequency = <50000000>;
882 + pinctrl-0 = <&usb0_pins>;
883 + pinctrl-names = "default";
889 + pinctrl-0 = <&usb1_pins>;
890 + pinctrl-names = "default";
896 + phys = <&usb3_phy0>;
907 + clock-frequency = <100000000>;
943 + pinctrl-0 = <&usb30_pins>;
944 + pinctrl-names = "default";
948 diff --git a/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
950 index 000000000000..3d1107f6d9cc
952 +++ b/arch/arm64/boot/dts/renesas/r8a77951-agl-refhw.dts
955 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
957 + * Copyright (C) 2019 Panasonic Corp.
958 + * Copyright (C) 2020 Konsulko Group
960 + * This file is licensed under the terms of the GNU General Public License
961 + * version 2. This program is licensed "as is" without any warranty of any
962 + * kind, whether express or implied.
966 + * This file is for the most part derived from:
968 + * - r8a77951-salvator-xs-4x2g.dts
969 + * - r8a77951-salvator-xs.dts
970 + * - salvator-xs.dtsi
972 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
976 +#include "r8a77951.dtsi"
977 +#include "agl-refhw-common.dtsi"
980 + model = "AGL Reference Hardware based on r8a77951 ES3.0+ with 8GiB (4 x 2 GiB)";
981 + compatible = "agl,refhw-h3", "renesas,r8a7795";
984 + device_type = "memory";
985 + /* first 128MB is reserved for secure area. */
986 + reg = <0x0 0x48000000 0x0 0x78000000>;
990 + device_type = "memory";
991 + reg = <0x5 0x00000000 0x0 0x80000000>;
995 + device_type = "memory";
996 + reg = <0x6 0x00000000 0x0 0x80000000>;
1000 + device_type = "memory";
1001 + reg = <0x7 0x00000000 0x0 0x80000000>;
1005 + #address-cells = <2>;
1006 + #size-cells = <2>;
1009 + /* device specific region for Lossy Decompression */
1010 + lossy_decompress: linux,lossy_decompress@54000000 {
1012 + reg = <0x00000000 0x54000000 0x0 0x03000000>;
1015 + /* For Audio DSP */
1016 + adsp_reserved: linux,adsp@57000000 {
1017 + compatible = "shared-dma-pool";
1019 + reg = <0x00000000 0x57000000 0x0 0x01000000>;
1022 + /* global autoconfigured region for contiguous allocations */
1023 + linux,cma@58000000 {
1024 + compatible = "shared-dma-pool";
1026 + reg = <0x00000000 0x58000000 0x0 0x18000000>;
1027 + linux,cma-default;
1030 + /* device specific region for contiguous allocations */
1031 + mmp_reserved: linux,multimedia@70000000 {
1032 + compatible = "shared-dma-pool";
1034 + reg = <0x00000000 0x70000000 0x0 0x10000000>;
1039 + compatible = "renesas,mmngr";
1040 + memory-region = <&mmp_reserved>, <&lossy_decompress>;
1044 + compatible = "renesas,mmngrbuf";
1048 + compatible = "renesas,vspm_if";
1053 + vga_in: endpoint {
1054 + /delete-property/remote-endpoint;
1062 + adv7123_in: endpoint {
1063 + /delete-property/remote-endpoint;
1068 + adv7123_out: endpoint {
1069 + /delete-property/remote-endpoint;
1079 + memory-region = <&adsp_reserved>;
1083 + clocks = <&cpg CPG_MOD 724>,
1084 + <&cpg CPG_MOD 723>,
1085 + <&cpg CPG_MOD 722>,
1086 + <&cpg CPG_MOD 721>,
1091 + clock-names = "du.0", "du.1", "du.2", "du.3",
1092 + "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1110 + dais = <&rsnd_port0 /* ak4613 */
1111 + &rsnd_port1 /* HDMI0 */
1112 + &rsnd_port2>; /* HDMI1 */
1121 + rcar_dw_hdmi0_out: endpoint {
1122 + remote-endpoint = <&hdmi0_con>;
1127 + dw_hdmi0_snd_in: endpoint {
1128 + remote-endpoint = <&rsnd_endpoint1>;
1135 + remote-endpoint = <&rcar_dw_hdmi0_out>;
1144 + rcar_dw_hdmi1_out: endpoint {
1145 + remote-endpoint = <&hdmi1_con>;
1150 + dw_hdmi1_snd_in: endpoint {
1151 + remote-endpoint = <&rsnd_endpoint2>;
1158 + remote-endpoint = <&rcar_dw_hdmi1_out>;
1172 + /* rsnd_port0 is on salvator-common */
1173 + rsnd_port1: port@1 {
1175 + rsnd_endpoint1: endpoint {
1176 + remote-endpoint = <&dw_hdmi0_snd_in>;
1178 + dai-format = "i2s";
1179 + bitclock-master = <&rsnd_endpoint1>;
1180 + frame-master = <&rsnd_endpoint1>;
1182 + playback = <&ssi2>;
1185 + rsnd_port2: port@2 {
1187 + rsnd_endpoint2: endpoint {
1188 + remote-endpoint = <&dw_hdmi1_snd_in>;
1190 + dai-format = "i2s";
1191 + bitclock-master = <&rsnd_endpoint2>;
1192 + frame-master = <&rsnd_endpoint2>;
1194 + playback = <&ssi3>;
1202 + groups = "usb2", "usb2_ovc";
1203 + function = "usb2";
1207 + * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1208 + * (when SW31 is the default setting on Salvator-XS).
1209 + * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1210 + * r8a77951 with Salvator-XS.
1211 + * Hence the SW31 setting must be changed like 2) below.
1212 + * 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1213 + * - Connect GP6_3[01] to ADV7842.
1214 + * 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1215 + * - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1216 + * - Connect GP6_{04,21} to ADV7842.
1218 + usb2_ch3_pins: usb2_ch3 {
1219 + groups = "usb2_ch3";
1220 + function = "usb2_ch3";
1225 + pinctrl-0 = <&usb2_pins>;
1226 + pinctrl-names = "default";
1232 + pinctrl-0 = <&usb2_ch3_pins>;
1233 + pinctrl-names = "default";
1254 +/* End r8a77951-salvator-xs.dts content */
1257 +/* Start r8a77951-salvator-xs-4x2g.dts content */
1260 + /* Map all possible DDR as inbound ranges */
1261 + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1265 + /* Map all possible DDR as inbound ranges */
1266 + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1269 +/* End r8a77951-salvator-xs-4x2g.dts content */
1272 +/* Start salvator-xs.dts content */
1275 + clock-frequency = <16640000>;
1279 + clock-frequency = <400000>;
1281 + versaclock6: clock-generator@6a {
1282 + compatible = "idt,5p49v6901";
1284 + #clock-cells = <1>;
1285 + clocks = <&x23_clk>;
1286 + clock-names = "xin";
1290 +/* End salvator-xs.dts content */
1293 +/* Start reference hardware specific tweaks */
1299 + /delete-property/remote-endpoint;
1305 + /delete-property/remote-endpoint;
1312 + status = "disabled";
1316 + status = "disabled";
1320 + clock-frequency = <0>;
1324 + /delete-property/ wp-gpios;
1329 + /delete-property/ wp-gpios;
1334 + /* Enable the CAN 1 & 2 transceivers */
1335 + can-1-transceiver-stb {
1337 + gpios = <21 GPIO_ACTIVE_HIGH>;
1340 + can-2-transceiver-stb {
1342 + gpios = <12 GPIO_ACTIVE_HIGH>;
1346 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1347 index fe156e8f88b8..da295b106561 100644
1348 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1349 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1350 @@ -97,6 +97,21 @@ static const struct adv748x_register_map adv748x_default_addresses[] = {
1351 [ADV748X_PAGE_TXA] = { "txa", 0x4a },
1354 +static const struct adv748x_register_map adv748x_default_addresses2[] = {
1355 + [ADV748X_PAGE_IO] = { "main", 0x71 },
1356 + [ADV748X_PAGE_DPLL] = { "dpll", 0x27 },
1357 + [ADV748X_PAGE_CP] = { "cp", 0x23 },
1358 + [ADV748X_PAGE_HDMI] = { "hdmi", 0x35 },
1359 + [ADV748X_PAGE_EDID] = { "edid", 0x37 },
1360 + [ADV748X_PAGE_REPEATER] = { "repeater", 0x33 },
1361 + [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x28 },
1362 + [ADV748X_PAGE_CBUS] = { "cbus", 0x29 },
1363 + [ADV748X_PAGE_CEC] = { "cec", 0x42 },
1364 + [ADV748X_PAGE_SDP] = { "sdp", 0x78 },
1365 + [ADV748X_PAGE_TXB] = { "txb", 0x49 },
1366 + [ADV748X_PAGE_TXA] = { "txa", 0x4b },
1369 static int adv748x_read_check(struct adv748x_state *state,
1370 int client_page, u8 reg)
1372 @@ -183,10 +198,17 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
1375 for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1376 - state->i2c_clients[i] = i2c_new_ancillary_device(
1377 + if ((state->client->addr << 1) == 0xe0) {
1378 + state->i2c_clients[i] = i2c_new_ancillary_device(
1380 adv748x_default_addresses[i].name,
1381 adv748x_default_addresses[i].default_addr);
1383 + state->i2c_clients[i] = i2c_new_ancillary_device(
1385 + adv748x_default_addresses2[i].name,
1386 + adv748x_default_addresses2[i].default_addr);
1389 if (IS_ERR(state->i2c_clients[i])) {
1390 adv_err(state, "failed to create i2c client %u\n", i);