meta-agl-refhw-gen3/recipes-kernel/linux/files/0001-add-agl-refhw.patch

   1 Add AGL reference hardware support
   2
   3 Upstream-Status: pending
   4
   5 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
   6 Signed-off-by: Raquel Medina <raquel.medina@konsulko.com>
   7 [asm330lhh interrupt fix]
   8 Signed-off-by: Hiroyuki Ishii <ishii.hiroyuki002@jp.panasonic.com>
   9
  10 ---
  11  arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi | 919 ++++++++++++++++++++++
  12  arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts | 392 +++++++++
  13  drivers/media/i2c/adv748x/adv748x-core.c          |  24 +-
  14  3 files changed, 1334 insertions(+), 1 deletion(-)
  15
  16 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  17 new file mode 100644
  18 index 000000000000..7474ed578c21
  19 --- /dev/null
  20 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  21 @@ -0,0 +1,919 @@
  22 +// SPDX-License-Identifier: GPL-2.0
  23 +/*
  24 + * Device Tree Source for common parts of AGL Reference Hardware board variants
  25 + *
  26 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
  27 + * Copyright (C) 2020 Konsulko Group
  28 + */
  29 +
  30 +/*
  31 + * This file is derived from salvator-common.dtsi
  32 + *
  33 + * It is currently unclear if the modifications made are such that they could
  34 + * be done on top of salvator-common.dtsi to allow removing the duplication.
  35 + * It is likely that the common pieces with salvator-common.dtsi would need to
  36 + * be factored out into a new common file, which is perhaps hard to justify.
  37 + */
  38 +
  39 +/*
  40 + * SSI-AK4613
  41 + *
  42 + * This command is required when Playback/Capture
  43 + *
  44 + *     amixer set "DVC Out" 100%
  45 + *     amixer set "DVC In" 100%
  46 + *
  47 + * You can use Mute
  48 + *
  49 + *     amixer set "DVC Out Mute" on
  50 + *     amixer set "DVC In Mute" on
  51 + *
  52 + * You can use Volume Ramp
  53 + *
  54 + *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  55 + *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  56 + *     amixer set "DVC Out Ramp" on
  57 + *     aplay xxx.wav &
  58 + *     amixer set "DVC Out"  80%  // Volume Down
  59 + *     amixer set "DVC Out" 100%  // Volume Up
  60 + */
  61 +
  62 +#include <dt-bindings/gpio/gpio.h>
  63 +
  64 +/ {
  65 +       aliases {
  66 +               serial0 = &scif2;
  67 +               serial1 = &scif1;
  68 +               serial2 = &scif5;
  69 +               serial3 = &hscif1;
  70 +               serial4 = &hscif0;
  71 +               serial5 = &hscif2;
  72 +               ethernet0 = &avb;
  73 +       };
  74 +
  75 +       chosen {
  76 +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  77 +               stdout-path = "serial0:115200n8";
  78 +       };
  79 +
  80 +       audio_clkout: audio-clkout {
  81 +               /*
  82 +                * This is same as <&rcar_sound 0>
  83 +                * but needed to avoid cs2000/rcar_sound probe dead-lock
  84 +                */
  85 +               compatible = "fixed-clock";
  86 +               #clock-cells = <0>;
  87 +               clock-frequency = <12288000>;
  88 +       };
  89 +
  90 +       avb-mch@ec5a0100 {
  91 +               compatible = "renesas,avb-mch-gen3";
  92 +               reg =   <0 0xec5a0100 0 0x100>;  /* ADG_AVB */
  93 +               reg-name = "adg_avb";
  94 +
  95 +               clocks = <&cpg CPG_MOD 922>;
  96 +               clock-names = "adg";
  97 +               resets = <&cpg 922>;
  98 +       };
  99 +
 100 +       hdmi0-in {
 101 +               compatible = "hdmi-connector";
 102 +               label = "HDMI0 IN";
 103 +               type = "a";
 104 +
 105 +               port {
 106 +                       hdmi_in_con: endpoint {
 107 +                               remote-endpoint = <&adv7481_hdmi>;
 108 +                       };
 109 +               };
 110 +       };
 111 +
 112 +       hdmi2-in {
 113 +               compatible = "hdmi-connector";
 114 +               label = "HDMI2 IN";
 115 +               type = "a";
 116 +
 117 +               port {
 118 +                       hdmi_in_con2: endpoint {
 119 +                               remote-endpoint = <&adv7481_hdmi2>;
 120 +                       };
 121 +               };
 122 +       };
 123 +
 124 +       reg_1p8v: regulator0 {
 125 +               compatible = "regulator-fixed";
 126 +               regulator-name = "fixed-1.8V";
 127 +               regulator-min-microvolt = <1800000>;
 128 +               regulator-max-microvolt = <1800000>;
 129 +               regulator-boot-on;
 130 +               regulator-always-on;
 131 +       };
 132 +
 133 +       reg_3p3v: regulator1 {
 134 +               compatible = "regulator-fixed";
 135 +               regulator-name = "fixed-3.3V";
 136 +               regulator-min-microvolt = <3300000>;
 137 +               regulator-max-microvolt = <3300000>;
 138 +               regulator-boot-on;
 139 +               regulator-always-on;
 140 +       };
 141 +
 142 +       reg_12v: regulator2 {
 143 +               compatible = "regulator-fixed";
 144 +               regulator-name = "fixed-12V";
 145 +               regulator-min-microvolt = <12000000>;
 146 +               regulator-max-microvolt = <12000000>;
 147 +               regulator-boot-on;
 148 +               regulator-always-on;
 149 +       };
 150 +
 151 +       sound_card: sound {
 152 +               compatible = "audio-graph-card";
 153 +
 154 +               label = "ak4613";
 155 +
 156 +               dais = <&rsnd_port0>;
 157 +       };
 158 +
 159 +       vcc_sdhi0: regulator-vcc-sdhi0 {
 160 +               compatible = "regulator-fixed";
 161 +
 162 +               regulator-name = "SDHI0 Vcc";
 163 +               regulator-min-microvolt = <3300000>;
 164 +               regulator-max-microvolt = <3300000>;
 165 +
 166 +               gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 167 +               enable-active-high;
 168 +       };
 169 +
 170 +       vccq_sdhi0: regulator-vccq-sdhi0 {
 171 +               compatible = "regulator-gpio";
 172 +
 173 +               regulator-name = "SDHI0 VccQ";
 174 +               regulator-min-microvolt = <1800000>;
 175 +               regulator-max-microvolt = <3300000>;
 176 +
 177 +               gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 178 +               gpios-states = <1>;
 179 +               states = <3300000 1
 180 +                         1800000 0>;
 181 +       };
 182 +
 183 +       vcc_sdhi3: regulator-vcc-sdhi3 {
 184 +               compatible = "regulator-fixed";
 185 +
 186 +               regulator-name = "SDHI3 Vcc";
 187 +               regulator-min-microvolt = <3300000>;
 188 +               regulator-max-microvolt = <3300000>;
 189 +
 190 +               gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 191 +               enable-active-high;
 192 +       };
 193 +
 194 +       vccq_sdhi3: regulator-vccq-sdhi3 {
 195 +               compatible = "regulator-gpio";
 196 +
 197 +               regulator-name = "SDHI3 VccQ";
 198 +               regulator-min-microvolt = <1800000>;
 199 +               regulator-max-microvolt = <3300000>;
 200 +
 201 +               gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 202 +               gpios-states = <1>;
 203 +               states = <3300000 1
 204 +                         1800000 0>;
 205 +       };
 206 +
 207 +       hdmi0-out {
 208 +               compatible = "hdmi-connector";
 209 +               label = "HDMI0 OUT";
 210 +               type = "a";
 211 +
 212 +               port {
 213 +                       hdmi0_con: endpoint {
 214 +                       };
 215 +               };
 216 +       };
 217 +
 218 +       hdmi1-out {
 219 +               compatible = "hdmi-connector";
 220 +               label = "HDMI1 OUT";
 221 +               type = "a";
 222 +
 223 +               port {
 224 +                       hdmi1_con: endpoint {
 225 +                       };
 226 +               };
 227 +       };
 228 +
 229 +       x12_clk: x12 {
 230 +               compatible = "fixed-clock";
 231 +               #clock-cells = <0>;
 232 +               clock-frequency = <24576000>;
 233 +       };
 234 +
 235 +       /* External DU dot clocks */
 236 +       x21_clk: x21-clock {
 237 +               compatible = "fixed-clock";
 238 +               #clock-cells = <0>;
 239 +               clock-frequency = <33000000>;
 240 +       };
 241 +
 242 +       x22_clk: x22-clock {
 243 +               compatible = "fixed-clock";
 244 +               #clock-cells = <0>;
 245 +               clock-frequency = <33000000>;
 246 +       };
 247 +
 248 +       x23_clk: x23-clock {
 249 +               compatible = "fixed-clock";
 250 +               #clock-cells = <0>;
 251 +               clock-frequency = <25000000>;
 252 +       };
 253 +};
 254 +
 255 +&a57_0 {
 256 +       cpu-supply = <&dvfs>;
 257 +};
 258 +
 259 +&audio_clk_a {
 260 +       clock-frequency = <22579200>;
 261 +};
 262 +
 263 +&avb {
 264 +       pinctrl-0 = <&avb_pins>;
 265 +       pinctrl-names = "default";
 266 +       phy-handle = <&phy0>;
 267 +       phy-mode = "rgmii-txid";
 268 +       status = "okay";
 269 +
 270 +       phy0: ethernet-phy@0 {
 271 +               rxc-skew-ps = <1500>;
 272 +               reg = <0>;
 273 +               interrupt-parent = <&gpio2>;
 274 +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 275 +               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 276 +       };
 277 +};
 278 +
 279 +&csi40 {
 280 +       status = "okay";
 281 +
 282 +       ports {
 283 +               port@0 {
 284 +                       reg = <0>;
 285 +
 286 +                       csi40_in: endpoint {
 287 +                               clock-lanes = <0>;
 288 +                               data-lanes = <1 2 3 4>;
 289 +                               remote-endpoint = <&adv7481_txa>;
 290 +                       };
 291 +               };
 292 +       };
 293 +};
 294 +
 295 +&csi41 {
 296 +       status = "okay";
 297 +
 298 +       ports {
 299 +               port@0 {
 300 +                       reg = <0>;
 301 +
 302 +                       csi41_in: endpoint {
 303 +                               clock-lanes = <0>;
 304 +                               data-lanes = <1 2 3 4>;
 305 +                               remote-endpoint = <&adv7481_txa2>;
 306 +                       };
 307 +               };
 308 +       };
 309 +};
 310 +
 311 +&du {
 312 +       status = "okay";
 313 +
 314 +};
 315 +
 316 +&ehci0 {
 317 +       dr_mode = "otg";
 318 +       status = "okay";
 319 +};
 320 +
 321 +&ehci1 {
 322 +       status = "okay";
 323 +};
 324 +
 325 +&extalr_clk {
 326 +       clock-frequency = <32768>;
 327 +};
 328 +
 329 +&hscif0 {
 330 +       pinctrl-0 = <&hscif0_pins>;
 331 +       pinctrl-names = "default";
 332 +       uart-has-rtscts;
 333 +
 334 +       status = "okay";
 335 +};
 336 +
 337 +&hscif1 {
 338 +       pinctrl-0 = <&hscif1_pins>;
 339 +       pinctrl-names = "default";
 340 +
 341 +       /* Please use exclusively to the scif1 node */
 342 +       status = "okay";
 343 +};
 344 +
 345 +&hscif2 {
 346 +       pinctrl-0 = <&hscif2_pins>;
 347 +       pinctrl-names = "default";
 348 +
 349 +       status = "okay";
 350 +};
 351 +
 352 +&hsusb {
 353 +       dr_mode = "otg";
 354 +       status = "okay";
 355 +};
 356 +
 357 +&i2c2 {
 358 +       pinctrl-0 = <&i2c2_pins>;
 359 +       pinctrl-names = "default";
 360 +
 361 +       status = "okay";
 362 +
 363 +       clock-frequency = <100000>;
 364 +
 365 +       video-receiver@70 {
 366 +               compatible = "adi,adv7481";
 367 +               reg = <0x70 0x26 0x22 0x34 0x36 0x32
 368 +                      0x31 0x30 0x41 0x79 0x4a 0x48>;
 369 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 370 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 371 +
 372 +               #address-cells = <1>;
 373 +               #size-cells = <0>;
 374 +
 375 +               interrupt-parent = <&gpio0>;
 376 +               interrupt-names = "intrq1", "intrq3";
 377 +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
 378 +                            <5 IRQ_TYPE_LEVEL_LOW>;
 379 +
 380 +               port@8 {
 381 +                       reg = <8>;
 382 +
 383 +                       adv7481_hdmi: endpoint {
 384 +                               remote-endpoint = <&hdmi_in_con>;
 385 +                       };
 386 +               };
 387 +
 388 +               port@a {
 389 +                       reg = <10>;
 390 +
 391 +                       adv7481_txa: endpoint {
 392 +                               clock-lanes = <0>;
 393 +                               data-lanes = <1 2 3 4>;
 394 +                               remote-endpoint = <&csi40_in>;
 395 +                       };
 396 +               };
 397 +
 398 +       };
 399 +
 400 +       video-receiver@71 {
 401 +               compatible = "adi,adv7481";
 402 +               reg = <0x71 0x27 0x23 0x35 0x37 0x33
 403 +                      0x28 0x29 0x42 0x78 0x4b 0x49>;
 404 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 405 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 406 +
 407 +               #address-cells = <1>;
 408 +               #size-cells = <0>;
 409 +
 410 +               interrupt-parent = <&gpio6>;
 411 +               interrupt-names = "intrq1", "intrq3";
 412 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
 413 +                            <1 IRQ_TYPE_LEVEL_LOW>;
 414 +
 415 +               port@8 {
 416 +                       reg = <8>;
 417 +
 418 +                       adv7481_hdmi2: endpoint {
 419 +                               remote-endpoint = <&hdmi_in_con2>;
 420 +                       };
 421 +               };
 422 +
 423 +               port@a {
 424 +                       reg = <10>;
 425 +
 426 +                       adv7481_txa2: endpoint {
 427 +                               clock-lanes = <0>;
 428 +                               data-lanes = <1 2 3 4>;
 429 +                               remote-endpoint = <&csi41_in>;
 430 +                       };
 431 +               };
 432 +       };
 433 +
 434 +       cs2000: clk_multiplier@4f {
 435 +               #clock-cells = <0>;
 436 +               compatible = "cirrus,cs2000-cp";
 437 +               reg = <0x4f>;
 438 +               clocks = <&audio_clkout>, <&x12_clk>;
 439 +               clock-names = "clk_in", "ref_clk";
 440 +
 441 +               assigned-clocks = <&cs2000>;
 442 +               assigned-clock-rates = <24576000>; /* 1/1 divide */
 443 +       };
 444 +};
 445 +
 446 +&i2c3 {
 447 +       pinctrl-0 = <&i2c3_pins>;
 448 +       pinctrl-names = "default";
 449 +
 450 +       status = "okay";
 451 +
 452 +       clock-frequency = <400000>;
 453 +
 454 +       asm330lhh@6a {
 455 +               compatible = "st,asm330lhh";
 456 +               reg = <0x6a>;
 457 +
 458 +               interrupt-names = "int1", "int2";
 459 +               interrupts-extended = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
 460 +                                     <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
 461 +               st,drdy-int-pin = <1>;
 462 +       };
 463 +};
 464 +
 465 +&i2c4 {
 466 +       status = "okay";
 467 +
 468 +       versaclock5: clock-generator@68 {
 469 +               compatible = "idt,9fgv0841";
 470 +               reg = <0x68>;
 471 +               #clock-cells = <1>;
 472 +               clocks = <&x23_clk>;
 473 +               clock-names = "xin";
 474 +       };
 475 +};
 476 +
 477 +&i2c5 {
 478 +       pinctrl-0 = <&i2c5_pins>;
 479 +       pinctrl-names = "default";
 480 +
 481 +       status = "okay";
 482 +
 483 +       clock-frequency = <100000>;
 484 +
 485 +       ak4613: codec@10 {
 486 +               compatible = "asahi-kasei,ak4613";
 487 +               #sound-dai-cells = <0>;
 488 +               reg = <0x10>;
 489 +               clocks = <&rcar_sound 3>;
 490 +
 491 +               asahi-kasei,in1-single-end;
 492 +               asahi-kasei,in2-single-end;
 493 +               asahi-kasei,out1-single-end;
 494 +               asahi-kasei,out2-single-end;
 495 +               asahi-kasei,out3-single-end;
 496 +               asahi-kasei,out4-single-end;
 497 +               asahi-kasei,out5-single-end;
 498 +               asahi-kasei,out6-single-end;
 499 +
 500 +               port {
 501 +                       ak4613_endpoint: endpoint {
 502 +                               remote-endpoint = <&rsnd_endpoint0>;
 503 +                       };
 504 +               };
 505 +       };
 506 +};
 507 +
 508 +&i2c_dvfs {
 509 +       status = "okay";
 510 +
 511 +       clock-frequency = <400000>;
 512 +
 513 +       pmic: pmic@30 {
 514 +               pinctrl-0 = <&irq0_pins>;
 515 +               pinctrl-names = "default";
 516 +
 517 +               compatible = "rohm,bd9571mwv";
 518 +               reg = <0x30>;
 519 +               interrupt-parent = <&intc_ex>;
 520 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 521 +               interrupt-controller;
 522 +               #interrupt-cells = <2>;
 523 +               gpio-controller;
 524 +               #gpio-cells = <2>;
 525 +               rohm,ddr-backup-power = <0xf>;
 526 +               rohm,rstbmode-level;
 527 +
 528 +               regulators {
 529 +                       dvfs: dvfs {
 530 +                               regulator-name = "dvfs";
 531 +                               regulator-min-microvolt = <750000>;
 532 +                               regulator-max-microvolt = <1030000>;
 533 +                               regulator-boot-on;
 534 +                               regulator-always-on;
 535 +                       };
 536 +               };
 537 +       };
 538 +
 539 +       eeprom@50 {
 540 +               compatible = "rohm,br24t01", "atmel,24c01";
 541 +               reg = <0x50>;
 542 +               pagesize = <8>;
 543 +       };
 544 +};
 545 +
 546 +&ohci0 {
 547 +       dr_mode = "otg";
 548 +       status = "okay";
 549 +};
 550 +
 551 +&ohci1 {
 552 +       status = "okay";
 553 +};
 554 +
 555 +&pcie_bus_clk {
 556 +       clock-frequency = <100000000>;
 557 +       status = "okay";
 558 +};
 559 +
 560 +&pciec0 {
 561 +       status = "okay";
 562 +};
 563 +
 564 +&pciec1 {
 565 +       status = "okay";
 566 +};
 567 +
 568 +&canfd {
 569 +       pinctrl-0 = <&canfd0_pins &canfd1_pins>;
 570 +       pinctrl-names = "default";
 571 +
 572 +       status = "okay";
 573 +
 574 +       channel0 {
 575 +               status = "okay";
 576 +       };
 577 +
 578 +       channel1 {
 579 +               status = "okay";
 580 +       };
 581 +};
 582 +
 583 +&pfc {
 584 +       pinctrl-0 = <&scif_clk_pins>;
 585 +       pinctrl-names = "default";
 586 +
 587 +       avb_pins: avb {
 588 +               mux {
 589 +                       groups = "avb_link", "avb_mdio", "avb_mii";
 590 +                       function = "avb";
 591 +               };
 592 +
 593 +               pins_mdio {
 594 +                       groups = "avb_mdio";
 595 +                       drive-strength = <24>;
 596 +               };
 597 +
 598 +               pins_mii_tx {
 599 +                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 600 +                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 601 +                       drive-strength = <12>;
 602 +               };
 603 +       };
 604 +
 605 +       hscif0_pins: hscif0 {
 606 +               groups = "hscif0_data", "hscif0_ctrl";
 607 +               function = "hscif0";
 608 +       };
 609 +
 610 +       hscif1_pins: hscif1 {
 611 +               groups = "hscif1_data_a";
 612 +               function = "hscif1";
 613 +       };
 614 +
 615 +       hscif2_pins: hscif2 {
 616 +               groups = "hscif2_data_c";
 617 +               function = "hscif2";
 618 +       };
 619 +
 620 +       i2c2_pins: i2c2 {
 621 +               groups = "i2c2_a";
 622 +               function = "i2c2";
 623 +       };
 624 +
 625 +       i2c3_pins: i2c3 {
 626 +               groups = "i2c3";
 627 +               function = "i2c3";
 628 +       };
 629 +
 630 +       i2c5_pins: i2c5 {
 631 +               groups = "i2c5";
 632 +               function = "i2c5";
 633 +       };
 634 +
 635 +       irq0_pins: irq0 {
 636 +               groups = "intc_ex_irq0";
 637 +               function = "intc_ex";
 638 +       };
 639 +
 640 +       scif1_pins: scif1 {
 641 +               groups = "scif1_data_b";
 642 +               function = "scif1";
 643 +       };
 644 +
 645 +       scif2_pins: scif2 {
 646 +               groups = "scif2_data_a";
 647 +               function = "scif2";
 648 +       };
 649 +
 650 +       scif5_pins: scif5 {
 651 +               groups = "scif5_data_a";
 652 +               function = "scif5";
 653 +       };
 654 +
 655 +       scif_clk_pins: scif_clk {
 656 +               groups = "scif_clk_a";
 657 +               function = "scif_clk";
 658 +       };
 659 +
 660 +       sdhi0_pins: sd0 {
 661 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 662 +               function = "sdhi0";
 663 +               power-source = <3300>;
 664 +       };
 665 +
 666 +       sdhi0_pins_uhs: sd0_uhs {
 667 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 668 +               function = "sdhi0";
 669 +               power-source = <1800>;
 670 +       };
 671 +
 672 +       sdhi2_pins: sd2 {
 673 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 674 +               function = "sdhi2";
 675 +               power-source = <3300>;
 676 +       };
 677 +
 678 +       sdhi2_pins_uhs: sd2_uhs {
 679 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 680 +               function = "sdhi2";
 681 +               power-source = <1800>;
 682 +       };
 683 +
 684 +       sdhi3_pins: sd3 {
 685 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 686 +               function = "sdhi3";
 687 +               power-source = <3300>;
 688 +       };
 689 +
 690 +       sdhi3_pins_uhs: sd3_uhs {
 691 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 692 +               function = "sdhi3";
 693 +               power-source = <1800>;
 694 +       };
 695 +
 696 +       sound_pins: sound {
 697 +               groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
 698 +               function = "ssi";
 699 +       };
 700 +
 701 +       sound_clk_pins: sound_clk {
 702 +               groups = "audio_clk_a_a", "audio_clk_b_a",
 703 +                        "audio_clkout_a", "audio_clkout3_b";
 704 +               function = "audio_clk";
 705 +       };
 706 +
 707 +       usb0_pins: usb0 {
 708 +               groups = "usb0";
 709 +               function = "usb0";
 710 +       };
 711 +
 712 +       usb1_pins: usb1 {
 713 +               groups = "usb1_ovc";
 714 +               function = "usb1";
 715 +       };
 716 +
 717 +       usb30_pins: usb30 {
 718 +               groups = "usb30", "usb30_ovc";
 719 +               function = "usb30";
 720 +       };
 721 +
 722 +       canfd0_pins: canfd0 {
 723 +               groups = "canfd0_data_a";
 724 +               function = "canfd0";
 725 +       };
 726 +
 727 +       canfd1_pins: canfd1 {
 728 +               groups = "canfd1_data";
 729 +               function = "canfd1";
 730 +       };
 731 +};
 732 +
 733 +&rcar_sound {
 734 +       pinctrl-0 = <&sound_pins &sound_clk_pins>;
 735 +       pinctrl-names = "default";
 736 +
 737 +       /* Single DAI */
 738 +       #sound-dai-cells = <0>;
 739 +
 740 +       /* audio_clkout0/1/2/3 */
 741 +       #clock-cells = <1>;
 742 +       clock-frequency = <12288000 11289600>;
 743 +
 744 +       status = "okay";
 745 +
 746 +       /* update <audio_clk_b> to <cs2000> */
 747 +       clocks = <&cpg CPG_MOD 1005>,
 748 +                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 749 +                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 750 +                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 751 +                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 752 +                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 753 +                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 754 +                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 755 +                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 756 +                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 757 +                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 758 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 759 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 760 +                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 761 +                <&audio_clk_a>, <&cs2000>,
 762 +                <&audio_clk_c>,
 763 +                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
 764 +
 765 +       ports {
 766 +               #address-cells = <1>;
 767 +               #size-cells = <0>;
 768 +               rsnd_port0: port@0 {
 769 +                       reg = <0>;
 770 +                       rsnd_endpoint0: endpoint {
 771 +                               remote-endpoint = <&ak4613_endpoint>;
 772 +
 773 +                               dai-format = "left_j";
 774 +                               bitclock-master = <&rsnd_endpoint0>;
 775 +                               frame-master = <&rsnd_endpoint0>;
 776 +
 777 +                               playback = <&ssi3>; //ssi0 -> ssi3
 778 +                               capture  = <&ssi4>; //ssi1 -> ssi4
 779 +                       };
 780 +               };
 781 +       };
 782 +};
 783 +
 784 +&rwdt {
 785 +       timeout-sec = <60>;
 786 +       status = "okay";
 787 +};
 788 +
 789 +&scif1 {
 790 +       pinctrl-0 = <&scif1_pins>;
 791 +       pinctrl-names = "default";
 792 +
 793 +       uart-has-rtscts;
 794 +       /* Please use exclusively to the hscif1 node */
 795 +       status = "okay";
 796 +};
 797 +
 798 +&scif2 {
 799 +       pinctrl-0 = <&scif2_pins>;
 800 +       pinctrl-names = "default";
 801 +
 802 +       status = "okay";
 803 +};
 804 +
 805 +&scif5 {
 806 +       pinctrl-0 = <&scif5_pins>;
 807 +       pinctrl-names = "default";
 808 +
 809 +       status = "okay";
 810 +};
 811 +
 812 +&scif_clk {
 813 +       clock-frequency = <14745600>;
 814 +};
 815 +
 816 +&sdhi0 {
 817 +       pinctrl-0 = <&sdhi0_pins>;
 818 +       pinctrl-1 = <&sdhi0_pins_uhs>;
 819 +       pinctrl-names = "default", "state_uhs";
 820 +
 821 +       vmmc-supply = <&vcc_sdhi0>;
 822 +       vqmmc-supply = <&vccq_sdhi0>;
 823 +       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 824 +       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 825 +       bus-width = <4>;
 826 +       sd-uhs-sdr50;
 827 +       sd-uhs-sdr104;
 828 +       status = "okay";
 829 +};
 830 +
 831 +&sdhi2 {
 832 +       /* used for on-board 8bit eMMC */
 833 +       pinctrl-0 = <&sdhi2_pins>;
 834 +       pinctrl-1 = <&sdhi2_pins_uhs>;
 835 +       pinctrl-names = "default", "state_uhs";
 836 +
 837 +       iommus = <&ipmmu_ds1 34>;
 838 +
 839 +       vmmc-supply = <&reg_3p3v>;
 840 +       vqmmc-supply = <&reg_1p8v>;
 841 +       bus-width = <8>;
 842 +       mmc-hs200-1_8v;
 843 +       mmc-hs400-1_8v;
 844 +       no-sd;
 845 +       no-sdio;
 846 +       non-removable;
 847 +       fixed-emmc-driver-type = <1>;
 848 +       status = "okay";
 849 +};
 850 +
 851 +&sdhi3 {
 852 +       pinctrl-0 = <&sdhi3_pins>;
 853 +       pinctrl-1 = <&sdhi3_pins_uhs>;
 854 +       pinctrl-names = "default", "state_uhs";
 855 +
 856 +       vmmc-supply = <&vcc_sdhi3>;
 857 +       vqmmc-supply = <&vccq_sdhi3>;
 858 +       cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 859 +       wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 860 +       bus-width = <4>;
 861 +       sd-uhs-sdr50;
 862 +       sd-uhs-sdr104;
 863 +       status = "okay";
 864 +};
 865 +
 866 +&ssi4 {
 867 +       shared-pin;
 868 +};
 869 +
 870 +&usb_extal_clk {
 871 +       clock-frequency = <50000000>;
 872 +};
 873 +
 874 +&usb2_phy0 {
 875 +       pinctrl-0 = <&usb0_pins>;
 876 +       pinctrl-names = "default";
 877 +
 878 +       status = "okay";
 879 +};
 880 +
 881 +&usb2_phy1 {
 882 +       pinctrl-0 = <&usb1_pins>;
 883 +       pinctrl-names = "default";
 884 +
 885 +       status = "okay";
 886 +};
 887 +
 888 +&usb3_peri0 {
 889 +       phys = <&usb3_phy0>;
 890 +       phy-names = "usb";
 891 +
 892 +       status = "okay";
 893 +};
 894 +
 895 +&usb3_phy0 {
 896 +       status = "okay";
 897 +};
 898 +
 899 +&usb3s0_clk {
 900 +       clock-frequency = <100000000>;
 901 +};
 902 +
 903 +&vin0 {
 904 +       status = "okay";
 905 +};
 906 +
 907 +&vin1 {
 908 +       status = "okay";
 909 +};
 910 +
 911 +&vin2 {
 912 +       status = "okay";
 913 +};
 914 +
 915 +&vin3 {
 916 +       status = "okay";
 917 +};
 918 +
 919 +&vin4 {
 920 +       status = "okay";
 921 +};
 922 +
 923 +&vin5 {
 924 +       status = "okay";
 925 +};
 926 +
 927 +&vin6 {
 928 +       status = "okay";
 929 +};
 930 +
 931 +&vin7 {
 932 +       status = "okay";
 933 +};
 934 +
 935 +&xhci0 {
 936 +       pinctrl-0 = <&usb30_pins>;
 937 +       pinctrl-names = "default";
 938 +
 939 +       status = "okay";
 940 +};
 941 diff --git a/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 942 new file mode 100644
 943 index 000000000000..6c846a94afe2
 944 --- /dev/null
 945 +++ b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 946 @@ -0,0 +1,392 @@
 947 +/*
 948 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
 949 + *
 950 + * Copyright (C) 2019 Panasonic Corp.
 951 + * Copyright (C) 2020 Konsulko Group
 952 + *
 953 + * This file is licensed under the terms of the GNU General Public License
 954 + * version 2.  This program is licensed "as is" without any warranty of any
 955 + * kind, whether express or implied.
 956 + */
 957 +
 958 +/*
 959 + * This file is for the most part derived from:
 960 + *
 961 + * - r8a7795-salvator-xs-4x2g.dts
 962 + * - r8a7795-salvator-xs.dts
 963 + * - salvator-xs.dtsi
 964 + *
 965 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
 966 + */
 967 +
 968 +/dts-v1/;
 969 +#include "r8a7795.dtsi"
 970 +#include "agl-refhw-common.dtsi"
 971 +
 972 +/ {
 973 +       model = "AGL Reference Hardware based on r8a7795 ES3.0+ with 8GiB (4 x 2 GiB)";
 974 +       compatible = "agl,refhw-h3", "renesas,r8a7795";
 975 +
 976 +       memory@48000000 {
 977 +               device_type = "memory";
 978 +               /* first 128MB is reserved for secure area. */
 979 +               reg = <0x0 0x48000000 0x0 0x78000000>;
 980 +       };
 981 +
 982 +       memory@500000000 {
 983 +               device_type = "memory";
 984 +               reg = <0x5 0x00000000 0x0 0x80000000>;
 985 +       };
 986 +
 987 +       memory@600000000 {
 988 +               device_type = "memory";
 989 +               reg = <0x6 0x00000000 0x0 0x80000000>;
 990 +       };
 991 +
 992 +       memory@700000000 {
 993 +               device_type = "memory";
 994 +               reg = <0x7 0x00000000 0x0 0x80000000>;
 995 +       };
 996 +
 997 +       reserved-memory {
 998 +               #address-cells = <2>;
 999 +               #size-cells = <2>;
1000 +               ranges;
1001 +
1002 +               /* device specific region for Lossy Decompression */
1003 +               lossy_decompress: linux,lossy_decompress@54000000 {
1004 +                       no-map;
1005 +                       reg = <0x00000000 0x54000000 0x0 0x03000000>;
1006 +               };
1007 +
1008 +               /* For Audio DSP */
1009 +               adsp_reserved: linux,adsp@57000000 {
1010 +                       compatible = "shared-dma-pool";
1011 +                       reusable;
1012 +                       reg = <0x00000000 0x57000000 0x0 0x01000000>;
1013 +               };
1014 +
1015 +               /* global autoconfigured region for contiguous allocations */
1016 +               linux,cma@58000000 {
1017 +                       compatible = "shared-dma-pool";
1018 +                       reusable;
1019 +                       reg = <0x00000000 0x58000000 0x0 0x18000000>;
1020 +                       linux,cma-default;
1021 +               };
1022 +
1023 +               /* device specific region for contiguous allocations */
1024 +               mmp_reserved: linux,multimedia@70000000 {
1025 +                       compatible = "shared-dma-pool";
1026 +                       reusable;
1027 +                       reg = <0x00000000 0x70000000 0x0 0x10000000>;
1028 +               };
1029 +       };
1030 +
1031 +       mmngr {
1032 +               compatible = "renesas,mmngr";
1033 +               memory-region = <&mmp_reserved>, <&lossy_decompress>;
1034 +       };
1035 +
1036 +       mmngrbuf {
1037 +               compatible = "renesas,mmngrbuf";
1038 +       };
1039 +
1040 +       vspm_if {
1041 +               compatible = "renesas,vspm_if";
1042 +       };
1043 +
1044 +       vga {
1045 +               port {
1046 +                       vga_in: endpoint {
1047 +                               /delete-property/remote-endpoint;
1048 +                       };
1049 +               };
1050 +       };
1051 +
1052 +       vga-encoder {
1053 +               ports {
1054 +                       port@0 {
1055 +                               adv7123_in: endpoint {
1056 +                                       /delete-property/remote-endpoint;
1057 +                               };
1058 +                       };
1059 +
1060 +                       port@1 {
1061 +                               adv7123_out: endpoint {
1062 +                                       /delete-property/remote-endpoint;
1063 +                               };
1064 +                       };
1065 +               };
1066 +       };
1067 +
1068 +};
1069 +
1070 +&adsp {
1071 +       status = "okay";
1072 +       memory-region = <&adsp_reserved>;
1073 +};
1074 +
1075 +&du {
1076 +       clocks = <&cpg CPG_MOD 724>,
1077 +                <&cpg CPG_MOD 723>,
1078 +                <&cpg CPG_MOD 722>,
1079 +                <&cpg CPG_MOD 721>,
1080 +                <&versaclock6 1>,
1081 +                <&x21_clk>,
1082 +                <&x22_clk>,
1083 +                <&versaclock6 2>;
1084 +       clock-names = "du.0", "du.1", "du.2", "du.3",
1085 +                     "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1086 +};
1087 +
1088 +&ehci2 {
1089 +       status = "okay";
1090 +};
1091 +
1092 +&ehci3 {
1093 +       dr_mode = "otg";
1094 +       status = "okay";
1095 +};
1096 +
1097 +&hsusb3 {
1098 +       dr_mode = "otg";
1099 +       status = "okay";
1100 +};
1101 +
1102 +&sound_card {
1103 +       dais = <&rsnd_port0     /* ak4613 */
1104 +               &rsnd_port1     /* HDMI0  */
1105 +               &rsnd_port2>;   /* HDMI1  */
1106 +};
1107 +
1108 +&hdmi0 {
1109 +       status = "okay";
1110 +
1111 +       ports {
1112 +               port@1 {
1113 +                       reg = <1>;
1114 +                       rcar_dw_hdmi0_out: endpoint {
1115 +                               remote-endpoint = <&hdmi0_con>;
1116 +                       };
1117 +               };
1118 +               port@2 {
1119 +                       reg = <2>;
1120 +                       dw_hdmi0_snd_in: endpoint {
1121 +                               remote-endpoint = <&rsnd_endpoint1>;
1122 +                       };
1123 +               };
1124 +       };
1125 +};
1126 +
1127 +&hdmi0_con {
1128 +       remote-endpoint = <&rcar_dw_hdmi0_out>;
1129 +};
1130 +
1131 +&hdmi1 {
1132 +       status = "okay";
1133 +
1134 +       ports {
1135 +               port@1 {
1136 +                       reg = <1>;
1137 +                       rcar_dw_hdmi1_out: endpoint {
1138 +                               remote-endpoint = <&hdmi1_con>;
1139 +                       };
1140 +               };
1141 +               port@2 {
1142 +                       reg = <2>;
1143 +                       dw_hdmi1_snd_in: endpoint {
1144 +                               remote-endpoint = <&rsnd_endpoint2>;
1145 +                       };
1146 +               };
1147 +       };
1148 +};
1149 +
1150 +&hdmi1_con {
1151 +       remote-endpoint = <&rcar_dw_hdmi1_out>;
1152 +};
1153 +
1154 +&ohci2 {
1155 +       status = "okay";
1156 +};
1157 +
1158 +&ohci3 {
1159 +       dr_mode = "otg";
1160 +       status = "okay";
1161 +};
1162 +
1163 +&rcar_sound {
1164 +       ports {
1165 +               /* rsnd_port0 is on salvator-common */
1166 +               rsnd_port1: port@1 {
1167 +                       reg = <1>;
1168 +                       rsnd_endpoint1: endpoint {
1169 +                               remote-endpoint = <&dw_hdmi0_snd_in>;
1170 +
1171 +                               dai-format = "i2s";
1172 +                               bitclock-master = <&rsnd_endpoint1>;
1173 +                               frame-master = <&rsnd_endpoint1>;
1174 +
1175 +                               playback = <&ssi2>;
1176 +                       };
1177 +               };
1178 +               rsnd_port2: port@2 {
1179 +                       reg = <2>;
1180 +                       rsnd_endpoint2: endpoint {
1181 +                               remote-endpoint = <&dw_hdmi1_snd_in>;
1182 +
1183 +                               dai-format = "i2s";
1184 +                               bitclock-master = <&rsnd_endpoint2>;
1185 +                               frame-master = <&rsnd_endpoint2>;
1186 +
1187 +                               playback = <&ssi3>;
1188 +                       };
1189 +               };
1190 +       };
1191 +};
1192 +
1193 +&pfc {
1194 +       usb2_pins: usb2 {
1195 +               groups = "usb2", "usb2_ovc";
1196 +               function = "usb2";
1197 +       };
1198 +
1199 +       /*
1200 +        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1201 +        *   (when SW31 is the default setting on Salvator-XS).
1202 +        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1203 +        *   r8a7795 with Salvator-XS.
1204 +        *   Hence the SW31 setting must be changed like 2) below.
1205 +        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1206 +        *      - Connect GP6_3[01] to ADV7842.
1207 +        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1208 +        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1209 +        *      - Connect GP6_{04,21} to ADV7842.
1210 +        */
1211 +       usb2_ch3_pins: usb2_ch3 {
1212 +               groups = "usb2_ch3";
1213 +               function = "usb2_ch3";
1214 +       };
1215 +};
1216 +
1217 +&usb2_phy2 {
1218 +       pinctrl-0 = <&usb2_pins>;
1219 +       pinctrl-names = "default";
1220 +
1221 +       status = "okay";
1222 +};
1223 +
1224 +&usb2_phy3 {
1225 +       pinctrl-0 = <&usb2_ch3_pins>;
1226 +       pinctrl-names = "default";
1227 +
1228 +       status = "okay";
1229 +};
1230 +
1231 +&vspbc {
1232 +       status = "okay";
1233 +};
1234 +
1235 +&vspbd {
1236 +       status = "okay";
1237 +};
1238 +
1239 +&vspi0 {
1240 +       status = "okay";
1241 +};
1242 +
1243 +&vspi1 {
1244 +       status = "okay";
1245 +};
1246 +
1247 +/* End r8a7795-salvator-xs.dts content */
1248 +
1249 +
1250 +/* Start r8a7795-salvator-xs-4x2g.dts content */
1251 +
1252 +&pciec0 {
1253 +       /* Map all possible DDR as inbound ranges */
1254 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1255 +};
1256 +
1257 +&pciec1 {
1258 +       /* Map all possible DDR as inbound ranges */
1259 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1260 +};
1261 +
1262 +/* End r8a7795-salvator-xs-4x2g.dts content */
1263 +
1264 +
1265 +/* Start salvator-xs.dts content */
1266 +
1267 +&extal_clk {
1268 +       clock-frequency = <16640000>;
1269 +};
1270 +
1271 +&i2c4 {
1272 +       clock-frequency = <400000>;
1273 +
1274 +       versaclock6: clock-generator@6a {
1275 +               compatible = "idt,5p49v6901";
1276 +               reg = <0x6a>;
1277 +               #clock-cells = <1>;
1278 +               clocks = <&x23_clk>;
1279 +               clock-names = "xin";
1280 +       };
1281 +};
1282 +
1283 +/* End salvator-xs.dts content */
1284 +
1285 +
1286 +/* Start reference hardware specific tweaks */
1287 +
1288 +&du {
1289 +       ports {
1290 +               port@0 {
1291 +                       endpoint {
1292 +                               /delete-property/remote-endpoint;
1293 +                       };
1294 +               };
1295 +
1296 +               port@3 {
1297 +                       endpoint {
1298 +                               /delete-property/remote-endpoint;
1299 +                       };
1300 +               };
1301 +       };
1302 +};
1303 +
1304 +&lvds0 {
1305 +       status = "disabled";
1306 +};
1307 +
1308 +&pwm1 {
1309 +       status = "disabled";
1310 +};
1311 +
1312 +&scif_clk {
1313 +       clock-frequency = <0>;
1314 +};
1315 +
1316 +&sdhi0 {
1317 +       /delete-property/ wp-gpios;
1318 +       non-removable;
1319 +};
1320 +
1321 +&sdhi3 {
1322 +       /delete-property/ wp-gpios;
1323 +       non-removable;
1324 +};
1325 +
1326 +&gpio6 {
1327 +       /* Enable the CAN 1 & 2 transceivers */
1328 +       can-1-transceiver-stb {
1329 +               gpio-hog;
1330 +               gpios = <21 GPIO_ACTIVE_HIGH>;
1331 +               output-low;
1332 +       };
1333 +       can-2-transceiver-stb {
1334 +               gpio-hog;
1335 +               gpios = <12 GPIO_ACTIVE_HIGH>;
1336 +               output-low;
1337 +       };
1338 +};
1339 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1340 index 87092ce5ba73..357c334113aa 100644
1341 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1342 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1343 @@ -97,6 +97,21 @@ static const struct adv748x_register_map adv748x_default_addresses[] = {
1344         [ADV748X_PAGE_TXA] = { "txa", 0x4a },
1345  };
1346
1347 +static const struct adv748x_register_map adv748x_default_addresses2[] = {
1348 +       [ADV748X_PAGE_IO] = { "main", 0x71 },
1349 +       [ADV748X_PAGE_DPLL] = { "dpll", 0x27 },
1350 +       [ADV748X_PAGE_CP] = { "cp", 0x23 },
1351 +       [ADV748X_PAGE_HDMI] = { "hdmi", 0x35 },
1352 +       [ADV748X_PAGE_EDID] = { "edid", 0x37 },
1353 +       [ADV748X_PAGE_REPEATER] = { "repeater", 0x33 },
1354 +       [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x28 },
1355 +       [ADV748X_PAGE_CBUS] = { "cbus", 0x29 },
1356 +       [ADV748X_PAGE_CEC] = { "cec", 0x42 },
1357 +       [ADV748X_PAGE_SDP] = { "sdp", 0x78 },
1358 +       [ADV748X_PAGE_TXB] = { "txb", 0x49 },
1359 +       [ADV748X_PAGE_TXA] = { "txa", 0x4b },
1360 +};
1361 +
1362  static int adv748x_read_check(struct adv748x_state *state,
1363                               int client_page, u8 reg)
1364  {
1365 @@ -183,10 +198,17 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
1366         int ret;
1367
1368         for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1369 -               state->i2c_clients[i] = i2c_new_ancillary_device(
1370 +               if ((state->client->addr << 1) == 0xe0) {
1371 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1372                                 state->client,
1373                                 adv748x_default_addresses[i].name,
1374                                 adv748x_default_addresses[i].default_addr);
1375 +               } else {
1376 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1377 +                               state->client,
1378 +                               adv748x_default_addresses2[i].name,
1379 +                               adv748x_default_addresses2[i].default_addr);
1380 +               }
1381
1382                 if (IS_ERR(state->i2c_clients[i])) {
1383                         adv_err(state, "failed to create i2c client %u\n", i);