meta-agl-refhw-gen3/recipes-kernel/linux/files/0001-add-agl-refhw.patch

   1 Add AGL reference hardware support
   2
   3 Upstream-Status: pending
   4
   5 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
   6
   7 ---
   8  arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi | 912 ++++++++++++++++++++++
   9  arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts | 378 +++++++++
  10  drivers/media/i2c/adv748x/adv748x-core.c          |  48 +-
  11  drivers/media/i2c/adv748x/adv748x.h               |  12 +
  12  4 files changed, 1346 insertions(+), 4 deletions(-)
  13
  14 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  15 new file mode 100644
  16 index 000000000000..a35cd24b27b9
  17 --- /dev/null
  18 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  19 @@ -0,0 +1,912 @@
  20 +// SPDX-License-Identifier: GPL-2.0
  21 +/*
  22 + * Device Tree Source for common parts of AGL Reference Hardware board variants
  23 + *
  24 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
  25 + * Copyright (C) 2020 Konsulko Group
  26 + */
  27 +
  28 +/*
  29 + * This file is derived from salvator-common.dtsi
  30 + *
  31 + * It is currently unclear if the modifications made are such that they could
  32 + * be done on top of salvator-common.dtsi to allow removing the duplication.
  33 + * It is likely that the common pieces with salvator-common.dtsi would need to
  34 + * be factored out into a new common file, which is perhaps hard to justify.
  35 + */
  36 +
  37 +/*
  38 + * SSI-AK4613
  39 + *
  40 + * This command is required when Playback/Capture
  41 + *
  42 + *     amixer set "DVC Out" 100%
  43 + *     amixer set "DVC In" 100%
  44 + *
  45 + * You can use Mute
  46 + *
  47 + *     amixer set "DVC Out Mute" on
  48 + *     amixer set "DVC In Mute" on
  49 + *
  50 + * You can use Volume Ramp
  51 + *
  52 + *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  53 + *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  54 + *     amixer set "DVC Out Ramp" on
  55 + *     aplay xxx.wav &
  56 + *     amixer set "DVC Out"  80%  // Volume Down
  57 + *     amixer set "DVC Out" 100%  // Volume Up
  58 + */
  59 +
  60 +#include <dt-bindings/gpio/gpio.h>
  61 +
  62 +/ {
  63 +       aliases {
  64 +               serial0 = &scif2;
  65 +               serial1 = &scif1;
  66 +               serial2 = &scif5;
  67 +               serial3 = &hscif1;
  68 +               serial4 = &hscif0;
  69 +               serial5 = &hscif2;
  70 +               ethernet0 = &avb;
  71 +       };
  72 +
  73 +       chosen {
  74 +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  75 +               stdout-path = "serial0:115200n8";
  76 +       };
  77 +
  78 +       audio_clkout: audio-clkout {
  79 +               /*
  80 +                * This is same as <&rcar_sound 0>
  81 +                * but needed to avoid cs2000/rcar_sound probe dead-lock
  82 +                */
  83 +               compatible = "fixed-clock";
  84 +               #clock-cells = <0>;
  85 +               clock-frequency = <12288000>;
  86 +       };
  87 +
  88 +       avb-mch@ec5a0100 {
  89 +               compatible = "renesas,avb-mch-gen3";
  90 +               reg =   <0 0xec5a0100 0 0x100>;  /* ADG_AVB */
  91 +               reg-name = "adg_avb";
  92 +
  93 +               clocks = <&cpg CPG_MOD 922>;
  94 +               clock-names = "adg";
  95 +               resets = <&cpg 922>;
  96 +       };
  97 +
  98 +       hdmi0-in {
  99 +               compatible = "hdmi-connector";
 100 +               label = "HDMI0 IN";
 101 +               type = "a";
 102 +
 103 +               port {
 104 +                       hdmi_in_con: endpoint {
 105 +                               remote-endpoint = <&adv7481_hdmi>;
 106 +                       };
 107 +               };
 108 +       };
 109 +
 110 +       hdmi2-in {
 111 +               compatible = "hdmi-connector";
 112 +               label = "HDMI2 IN";
 113 +               type = "a";
 114 +
 115 +               port {
 116 +                       hdmi_in_con2: endpoint {
 117 +                               remote-endpoint = <&adv7481_hdmi2>;
 118 +                       };
 119 +               };
 120 +       };
 121 +
 122 +       reg_1p8v: regulator0 {
 123 +               compatible = "regulator-fixed";
 124 +               regulator-name = "fixed-1.8V";
 125 +               regulator-min-microvolt = <1800000>;
 126 +               regulator-max-microvolt = <1800000>;
 127 +               regulator-boot-on;
 128 +               regulator-always-on;
 129 +       };
 130 +
 131 +       reg_3p3v: regulator1 {
 132 +               compatible = "regulator-fixed";
 133 +               regulator-name = "fixed-3.3V";
 134 +               regulator-min-microvolt = <3300000>;
 135 +               regulator-max-microvolt = <3300000>;
 136 +               regulator-boot-on;
 137 +               regulator-always-on;
 138 +       };
 139 +
 140 +       reg_12v: regulator2 {
 141 +               compatible = "regulator-fixed";
 142 +               regulator-name = "fixed-12V";
 143 +               regulator-min-microvolt = <12000000>;
 144 +               regulator-max-microvolt = <12000000>;
 145 +               regulator-boot-on;
 146 +               regulator-always-on;
 147 +       };
 148 +
 149 +       sound_card: sound {
 150 +               compatible = "audio-graph-card";
 151 +
 152 +               label = "rcar-sound";
 153 +
 154 +               dais = <&rsnd_port0>;
 155 +       };
 156 +
 157 +       vcc_sdhi0: regulator-vcc-sdhi0 {
 158 +               compatible = "regulator-fixed";
 159 +
 160 +               regulator-name = "SDHI0 Vcc";
 161 +               regulator-min-microvolt = <3300000>;
 162 +               regulator-max-microvolt = <3300000>;
 163 +
 164 +               gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 165 +               enable-active-high;
 166 +       };
 167 +
 168 +       vccq_sdhi0: regulator-vccq-sdhi0 {
 169 +               compatible = "regulator-gpio";
 170 +
 171 +               regulator-name = "SDHI0 VccQ";
 172 +               regulator-min-microvolt = <1800000>;
 173 +               regulator-max-microvolt = <3300000>;
 174 +
 175 +               gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 176 +               gpios-states = <1>;
 177 +               states = <3300000 1
 178 +                         1800000 0>;
 179 +       };
 180 +
 181 +       vcc_sdhi3: regulator-vcc-sdhi3 {
 182 +               compatible = "regulator-fixed";
 183 +
 184 +               regulator-name = "SDHI3 Vcc";
 185 +               regulator-min-microvolt = <3300000>;
 186 +               regulator-max-microvolt = <3300000>;
 187 +
 188 +               gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 189 +               enable-active-high;
 190 +       };
 191 +
 192 +       vccq_sdhi3: regulator-vccq-sdhi3 {
 193 +               compatible = "regulator-gpio";
 194 +
 195 +               regulator-name = "SDHI3 VccQ";
 196 +               regulator-min-microvolt = <1800000>;
 197 +               regulator-max-microvolt = <3300000>;
 198 +
 199 +               gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 200 +               gpios-states = <1>;
 201 +               states = <3300000 1
 202 +                         1800000 0>;
 203 +       };
 204 +
 205 +       hdmi0-out {
 206 +               compatible = "hdmi-connector";
 207 +               label = "HDMI0 OUT";
 208 +               type = "a";
 209 +
 210 +               port {
 211 +                       hdmi0_con: endpoint {
 212 +                       };
 213 +               };
 214 +       };
 215 +
 216 +       hdmi1-out {
 217 +               compatible = "hdmi-connector";
 218 +               label = "HDMI1 OUT";
 219 +               type = "a";
 220 +
 221 +               port {
 222 +                       hdmi1_con: endpoint {
 223 +                       };
 224 +               };
 225 +       };
 226 +
 227 +       x12_clk: x12 {
 228 +               compatible = "fixed-clock";
 229 +               #clock-cells = <0>;
 230 +               clock-frequency = <24576000>;
 231 +       };
 232 +
 233 +       /* External DU dot clocks */
 234 +       x21_clk: x21-clock {
 235 +               compatible = "fixed-clock";
 236 +               #clock-cells = <0>;
 237 +               clock-frequency = <33000000>;
 238 +       };
 239 +
 240 +       x22_clk: x22-clock {
 241 +               compatible = "fixed-clock";
 242 +               #clock-cells = <0>;
 243 +               clock-frequency = <33000000>;
 244 +       };
 245 +
 246 +       x23_clk: x23-clock {
 247 +               compatible = "fixed-clock";
 248 +               #clock-cells = <0>;
 249 +               clock-frequency = <25000000>;
 250 +       };
 251 +};
 252 +
 253 +&a57_0 {
 254 +       cpu-supply = <&dvfs>;
 255 +};
 256 +
 257 +&audio_clk_a {
 258 +       clock-frequency = <22579200>;
 259 +};
 260 +
 261 +&avb {
 262 +       pinctrl-0 = <&avb_pins>;
 263 +       pinctrl-names = "default";
 264 +       phy-handle = <&phy0>;
 265 +       phy-mode = "rgmii-txid";
 266 +       status = "okay";
 267 +
 268 +       phy0: ethernet-phy@0 {
 269 +               rxc-skew-ps = <1500>;
 270 +               reg = <0>;
 271 +               interrupt-parent = <&gpio2>;
 272 +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 273 +               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 274 +       };
 275 +};
 276 +
 277 +&csi40 {
 278 +       status = "okay";
 279 +
 280 +       ports {
 281 +               port@0 {
 282 +                       reg = <0>;
 283 +
 284 +                       csi40_in: endpoint {
 285 +                               clock-lanes = <0>;
 286 +                               data-lanes = <1 2 3 4>;
 287 +                               remote-endpoint = <&adv7481_txa>;
 288 +                       };
 289 +               };
 290 +       };
 291 +};
 292 +
 293 +&csi41 {
 294 +       status = "okay";
 295 +
 296 +       ports {
 297 +               port@0 {
 298 +                       reg = <0>;
 299 +
 300 +                       csi41_in: endpoint {
 301 +                               clock-lanes = <0>;
 302 +                               data-lanes = <1 2 3 4>;
 303 +                               remote-endpoint = <&adv7481_txa2>;
 304 +                       };
 305 +               };
 306 +       };
 307 +};
 308 +
 309 +&du {
 310 +       status = "okay";
 311 +
 312 +};
 313 +
 314 +&ehci0 {
 315 +       dr_mode = "otg";
 316 +       status = "okay";
 317 +};
 318 +
 319 +&ehci1 {
 320 +       status = "okay";
 321 +};
 322 +
 323 +&extalr_clk {
 324 +       clock-frequency = <32768>;
 325 +};
 326 +
 327 +&hscif0 {
 328 +       pinctrl-0 = <&hscif0_pins>;
 329 +       pinctrl-names = "default";
 330 +       uart-has-rtscts;
 331 +
 332 +       status = "okay";
 333 +};
 334 +
 335 +&hscif1 {
 336 +       pinctrl-0 = <&hscif1_pins>;
 337 +       pinctrl-names = "default";
 338 +
 339 +       /* Please use exclusively to the scif1 node */
 340 +       status = "okay";
 341 +};
 342 +
 343 +&hscif2 {
 344 +       pinctrl-0 = <&hscif2_pins>;
 345 +       pinctrl-names = "default";
 346 +
 347 +       status = "okay";
 348 +};
 349 +
 350 +&hsusb {
 351 +       dr_mode = "otg";
 352 +       status = "okay";
 353 +};
 354 +
 355 +&i2c2 {
 356 +       pinctrl-0 = <&i2c2_pins>;
 357 +       pinctrl-names = "default";
 358 +
 359 +       status = "okay";
 360 +
 361 +       clock-frequency = <100000>;
 362 +
 363 +       video-receiver@70 {
 364 +               compatible = "adi,adv7481";
 365 +               reg = <0x70>;
 366 +
 367 +               #address-cells = <1>;
 368 +               #size-cells = <0>;
 369 +
 370 +               interrupt-parent = <&gpio0>;
 371 +               interrupt-names = "intrq1", "intrq3";
 372 +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
 373 +                            <5 IRQ_TYPE_LEVEL_LOW>;
 374 +
 375 +               port@8 {
 376 +                       reg = <8>;
 377 +
 378 +                       adv7481_hdmi: endpoint {
 379 +                               remote-endpoint = <&hdmi_in_con>;
 380 +                       };
 381 +               };
 382 +
 383 +               port@a {
 384 +                       reg = <10>;
 385 +
 386 +                       adv7481_txa: endpoint {
 387 +                               clock-lanes = <0>;
 388 +                               data-lanes = <1 2 3 4>;
 389 +                               remote-endpoint = <&csi40_in>;
 390 +                       };
 391 +               };
 392 +
 393 +       };
 394 +
 395 +       video-receiver@71 {
 396 +               compatible = "adi,adv7481";
 397 +               reg = <0x71>;
 398 +
 399 +               #address-cells = <1>;
 400 +               #size-cells = <0>;
 401 +
 402 +               interrupt-parent = <&gpio6>;
 403 +               interrupt-names = "intrq1", "intrq3";
 404 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
 405 +                            <1 IRQ_TYPE_LEVEL_LOW>;
 406 +
 407 +               port@8 {
 408 +                       reg = <8>;
 409 +
 410 +                       adv7481_hdmi2: endpoint {
 411 +                               remote-endpoint = <&hdmi_in_con2>;
 412 +                       };
 413 +               };
 414 +
 415 +               port@a {
 416 +                       reg = <10>;
 417 +
 418 +                       adv7481_txa2: endpoint {
 419 +                               clock-lanes = <0>;
 420 +                               data-lanes = <1 2 3 4>;
 421 +                               remote-endpoint = <&csi41_in>;
 422 +                       };
 423 +               };
 424 +       };
 425 +
 426 +       cs2000: clk_multiplier@4f {
 427 +               #clock-cells = <0>;
 428 +               compatible = "cirrus,cs2000-cp";
 429 +               reg = <0x4f>;
 430 +               clocks = <&audio_clkout>, <&x12_clk>;
 431 +               clock-names = "clk_in", "ref_clk";
 432 +
 433 +               assigned-clocks = <&cs2000>;
 434 +               assigned-clock-rates = <24576000>; /* 1/1 divide */
 435 +       };
 436 +};
 437 +
 438 +&i2c3 {
 439 +       pinctrl-0 = <&i2c3_pins>;
 440 +       pinctrl-names = "default";
 441 +
 442 +       status = "okay";
 443 +
 444 +       clock-frequency = <100000>;
 445 +
 446 +       asm330lhh@6a {
 447 +               compatible = "st,asm330lhh";
 448 +               reg = <0x6a>;
 449 +
 450 +               interrupt-names = "int1", "int2";
 451 +               interrupts = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
 452 +                            <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
 453 +       };
 454 +};
 455 +
 456 +&i2c4 {
 457 +       status = "okay";
 458 +
 459 +       versaclock5: clock-generator@68 {
 460 +               compatible = "idt,9fgv0841";
 461 +               reg = <0x68>;
 462 +               #clock-cells = <1>;
 463 +               clocks = <&x23_clk>;
 464 +               clock-names = "xin";
 465 +       };
 466 +};
 467 +
 468 +&i2c5 {
 469 +       pinctrl-0 = <&i2c5_pins>;
 470 +       pinctrl-names = "default";
 471 +
 472 +       status = "okay";
 473 +
 474 +       clock-frequency = <100000>;
 475 +
 476 +       ak4613: codec@10 {
 477 +               compatible = "asahi-kasei,ak4613";
 478 +               #sound-dai-cells = <0>;
 479 +               reg = <0x10>;
 480 +               clocks = <&rcar_sound 3>;
 481 +
 482 +               asahi-kasei,in1-single-end;
 483 +               asahi-kasei,in2-single-end;
 484 +               asahi-kasei,out1-single-end;
 485 +               asahi-kasei,out2-single-end;
 486 +               asahi-kasei,out3-single-end;
 487 +               asahi-kasei,out4-single-end;
 488 +               asahi-kasei,out5-single-end;
 489 +               asahi-kasei,out6-single-end;
 490 +
 491 +               port {
 492 +                       ak4613_endpoint: endpoint {
 493 +                               remote-endpoint = <&rsnd_endpoint0>;
 494 +                       };
 495 +               };
 496 +       };
 497 +};
 498 +
 499 +&i2c_dvfs {
 500 +       status = "okay";
 501 +
 502 +       clock-frequency = <400000>;
 503 +
 504 +       pmic: pmic@30 {
 505 +               pinctrl-0 = <&irq0_pins>;
 506 +               pinctrl-names = "default";
 507 +
 508 +               compatible = "rohm,bd9571mwv";
 509 +               reg = <0x30>;
 510 +               interrupt-parent = <&intc_ex>;
 511 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 512 +               interrupt-controller;
 513 +               #interrupt-cells = <2>;
 514 +               gpio-controller;
 515 +               #gpio-cells = <2>;
 516 +               rohm,ddr-backup-power = <0xf>;
 517 +               rohm,rstbmode-level;
 518 +
 519 +               regulators {
 520 +                       dvfs: dvfs {
 521 +                               regulator-name = "dvfs";
 522 +                               regulator-min-microvolt = <750000>;
 523 +                               regulator-max-microvolt = <1030000>;
 524 +                               regulator-boot-on;
 525 +                               regulator-always-on;
 526 +                       };
 527 +               };
 528 +       };
 529 +
 530 +       eeprom@50 {
 531 +               compatible = "rohm,br24t01", "atmel,24c01";
 532 +               reg = <0x50>;
 533 +               pagesize = <8>;
 534 +       };
 535 +};
 536 +
 537 +&ohci0 {
 538 +       dr_mode = "otg";
 539 +       status = "okay";
 540 +};
 541 +
 542 +&ohci1 {
 543 +       status = "okay";
 544 +};
 545 +
 546 +&pcie_bus_clk {
 547 +       clock-frequency = <100000000>;
 548 +       status = "okay";
 549 +};
 550 +
 551 +&pciec0 {
 552 +       status = "okay";
 553 +};
 554 +
 555 +&pciec1 {
 556 +       status = "okay";
 557 +};
 558 +
 559 +&canfd {
 560 +       pinctrl-0 = <&canfd0_pins &canfd1_pins>;
 561 +       pinctrl-names = "default";
 562 +
 563 +       status = "okay";
 564 +
 565 +       channel0 {
 566 +               status = "okay";
 567 +       };
 568 +
 569 +       channel1 {
 570 +               status = "okay";
 571 +       };
 572 +};
 573 +
 574 +&pfc {
 575 +       pinctrl-0 = <&scif_clk_pins>;
 576 +       pinctrl-names = "default";
 577 +
 578 +       avb_pins: avb {
 579 +               mux {
 580 +                       groups = "avb_link", "avb_mdio", "avb_mii";
 581 +                       function = "avb";
 582 +               };
 583 +
 584 +               pins_mdio {
 585 +                       groups = "avb_mdio";
 586 +                       drive-strength = <24>;
 587 +               };
 588 +
 589 +               pins_mii_tx {
 590 +                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 591 +                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 592 +                       drive-strength = <12>;
 593 +               };
 594 +       };
 595 +
 596 +       hscif0_pins: hscif0 {
 597 +               groups = "hscif0_data", "hscif0_ctrl";
 598 +               function = "hscif0";
 599 +       };
 600 +
 601 +       hscif1_pins: hscif1 {
 602 +               groups = "hscif1_data_a";
 603 +               function = "hscif1";
 604 +       };
 605 +
 606 +       hscif2_pins: hscif2 {
 607 +               groups = "hscif2_data_c";
 608 +               function = "hscif2";
 609 +       };
 610 +
 611 +       i2c2_pins: i2c2 {
 612 +               groups = "i2c2_a";
 613 +               function = "i2c2";
 614 +       };
 615 +
 616 +       i2c3_pins: i2c3 {
 617 +               groups = "i2c3";
 618 +               function = "i2c3";
 619 +       };
 620 +
 621 +       i2c5_pins: i2c5 {
 622 +               groups = "i2c5";
 623 +               function = "i2c5";
 624 +       };
 625 +
 626 +       irq0_pins: irq0 {
 627 +               groups = "intc_ex_irq0";
 628 +               function = "intc_ex";
 629 +       };
 630 +
 631 +       scif1_pins: scif1 {
 632 +               groups = "scif1_data_b";
 633 +               function = "scif1";
 634 +       };
 635 +
 636 +       scif2_pins: scif2 {
 637 +               groups = "scif2_data_a";
 638 +               function = "scif2";
 639 +       };
 640 +
 641 +       scif5_pins: scif5 {
 642 +               groups = "scif5_data_a";
 643 +               function = "scif5";
 644 +       };
 645 +
 646 +       scif_clk_pins: scif_clk {
 647 +               groups = "scif_clk_a";
 648 +               function = "scif_clk";
 649 +       };
 650 +
 651 +       sdhi0_pins: sd0 {
 652 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 653 +               function = "sdhi0";
 654 +               power-source = <3300>;
 655 +       };
 656 +
 657 +       sdhi0_pins_uhs: sd0_uhs {
 658 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 659 +               function = "sdhi0";
 660 +               power-source = <1800>;
 661 +       };
 662 +
 663 +       sdhi2_pins: sd2 {
 664 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 665 +               function = "sdhi2";
 666 +               power-source = <3300>;
 667 +       };
 668 +
 669 +       sdhi2_pins_uhs: sd2_uhs {
 670 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 671 +               function = "sdhi2";
 672 +               power-source = <1800>;
 673 +       };
 674 +
 675 +       sdhi3_pins: sd3 {
 676 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 677 +               function = "sdhi3";
 678 +               power-source = <3300>;
 679 +       };
 680 +
 681 +       sdhi3_pins_uhs: sd3_uhs {
 682 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 683 +               function = "sdhi3";
 684 +               power-source = <1800>;
 685 +       };
 686 +
 687 +       sound_pins: sound {
 688 +               groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
 689 +               function = "ssi";
 690 +       };
 691 +
 692 +       sound_clk_pins: sound_clk {
 693 +               groups = "audio_clk_a_a", "audio_clk_b_a",
 694 +                        "audio_clkout_a", "audio_clkout3_b";
 695 +               function = "audio_clk";
 696 +       };
 697 +
 698 +       usb0_pins: usb0 {
 699 +               groups = "usb0";
 700 +               function = "usb0";
 701 +       };
 702 +
 703 +       usb1_pins: usb1 {
 704 +               groups = "usb1";
 705 +               function = "usb1";
 706 +       };
 707 +
 708 +       usb30_pins: usb30 {
 709 +               groups = "usb30", "usb30_ovc";
 710 +               function = "usb30";
 711 +       };
 712 +
 713 +       canfd0_pins: canfd0 {
 714 +               groups = "canfd0_data_a";
 715 +               function = "canfd0";
 716 +       };
 717 +
 718 +       canfd1_pins: canfd1 {
 719 +               groups = "canfd1_data";
 720 +               function = "canfd1";
 721 +       };
 722 +};
 723 +
 724 +&rcar_sound {
 725 +       pinctrl-0 = <&sound_pins &sound_clk_pins>;
 726 +       pinctrl-names = "default";
 727 +
 728 +       /* Single DAI */
 729 +       #sound-dai-cells = <0>;
 730 +
 731 +       /* audio_clkout0/1/2/3 */
 732 +       #clock-cells = <1>;
 733 +       clock-frequency = <12288000 11289600>;
 734 +
 735 +       status = "okay";
 736 +
 737 +       /* update <audio_clk_b> to <cs2000> */
 738 +       clocks = <&cpg CPG_MOD 1005>,
 739 +                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 740 +                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 741 +                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 742 +                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 743 +                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 744 +                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 745 +                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 746 +                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 747 +                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 748 +                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 749 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 750 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 751 +                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 752 +                <&audio_clk_a>, <&cs2000>,
 753 +                <&audio_clk_c>,
 754 +                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
 755 +
 756 +       ports {
 757 +               #address-cells = <1>;
 758 +               #size-cells = <0>;
 759 +               rsnd_port0: port@0 {
 760 +                       reg = <0>;
 761 +                       rsnd_endpoint0: endpoint {
 762 +                               remote-endpoint = <&ak4613_endpoint>;
 763 +
 764 +                               dai-format = "left_j";
 765 +                               bitclock-master = <&rsnd_endpoint0>;
 766 +                               frame-master = <&rsnd_endpoint0>;
 767 +
 768 +                               playback = <&ssi3>; //ssi0 -> ssi3
 769 +                               capture  = <&ssi4>; //ssi1 -> ssi4
 770 +                       };
 771 +               };
 772 +       };
 773 +};
 774 +
 775 +&rwdt {
 776 +       timeout-sec = <60>;
 777 +       status = "okay";
 778 +};
 779 +
 780 +&scif1 {
 781 +       pinctrl-0 = <&scif1_pins>;
 782 +       pinctrl-names = "default";
 783 +
 784 +       uart-has-rtscts;
 785 +       /* Please use exclusively to the hscif1 node */
 786 +       status = "okay";
 787 +};
 788 +
 789 +&scif2 {
 790 +       pinctrl-0 = <&scif2_pins>;
 791 +       pinctrl-names = "default";
 792 +
 793 +       status = "okay";
 794 +};
 795 +
 796 +&scif5 {
 797 +       pinctrl-0 = <&scif5_pins>;
 798 +       pinctrl-names = "default";
 799 +
 800 +       status = "okay";
 801 +};
 802 +
 803 +&scif_clk {
 804 +       clock-frequency = <14745600>;
 805 +};
 806 +
 807 +&sdhi0 {
 808 +       pinctrl-0 = <&sdhi0_pins>;
 809 +       pinctrl-1 = <&sdhi0_pins_uhs>;
 810 +       pinctrl-names = "default", "state_uhs";
 811 +
 812 +       vmmc-supply = <&vcc_sdhi0>;
 813 +       vqmmc-supply = <&vccq_sdhi0>;
 814 +       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 815 +       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 816 +       bus-width = <4>;
 817 +       sd-uhs-sdr50;
 818 +       sd-uhs-sdr104;
 819 +       status = "okay";
 820 +};
 821 +
 822 +&sdhi2 {
 823 +       /* used for on-board 8bit eMMC */
 824 +       pinctrl-0 = <&sdhi2_pins>;
 825 +       pinctrl-1 = <&sdhi2_pins_uhs>;
 826 +       pinctrl-names = "default", "state_uhs";
 827 +
 828 +       iommus = <&ipmmu_ds1 34>;
 829 +
 830 +       vmmc-supply = <&reg_3p3v>;
 831 +       vqmmc-supply = <&reg_1p8v>;
 832 +       bus-width = <8>;
 833 +       mmc-hs200-1_8v;
 834 +       mmc-hs400-1_8v;
 835 +       no-sd;
 836 +       no-sdio;
 837 +       non-removable;
 838 +       fixed-emmc-driver-type = <1>;
 839 +       status = "okay";
 840 +};
 841 +
 842 +&sdhi3 {
 843 +       pinctrl-0 = <&sdhi3_pins>;
 844 +       pinctrl-1 = <&sdhi3_pins_uhs>;
 845 +       pinctrl-names = "default", "state_uhs";
 846 +
 847 +       vmmc-supply = <&vcc_sdhi3>;
 848 +       vqmmc-supply = <&vccq_sdhi3>;
 849 +       cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 850 +       wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 851 +       bus-width = <4>;
 852 +       sd-uhs-sdr50;
 853 +       sd-uhs-sdr104;
 854 +       status = "okay";
 855 +};
 856 +
 857 +&ssi4 {
 858 +       shared-pin;
 859 +};
 860 +
 861 +&usb_extal_clk {
 862 +       clock-frequency = <50000000>;
 863 +};
 864 +
 865 +&usb2_phy0 {
 866 +       pinctrl-0 = <&usb0_pins>;
 867 +       pinctrl-names = "default";
 868 +
 869 +       status = "okay";
 870 +};
 871 +
 872 +&usb2_phy1 {
 873 +       pinctrl-0 = <&usb1_pins>;
 874 +       pinctrl-names = "default";
 875 +
 876 +       status = "okay";
 877 +};
 878 +
 879 +&usb3_peri0 {
 880 +       phys = <&usb3_phy0>;
 881 +       phy-names = "usb";
 882 +
 883 +       status = "okay";
 884 +};
 885 +
 886 +&usb3_phy0 {
 887 +       status = "okay";
 888 +};
 889 +
 890 +&usb3s0_clk {
 891 +       clock-frequency = <100000000>;
 892 +};
 893 +
 894 +&vin0 {
 895 +       status = "okay";
 896 +};
 897 +
 898 +&vin1 {
 899 +       status = "okay";
 900 +};
 901 +
 902 +&vin2 {
 903 +       status = "okay";
 904 +};
 905 +
 906 +&vin3 {
 907 +       status = "okay";
 908 +};
 909 +
 910 +&vin4 {
 911 +       status = "okay";
 912 +};
 913 +
 914 +&vin5 {
 915 +       status = "okay";
 916 +};
 917 +
 918 +&vin6 {
 919 +       status = "okay";
 920 +};
 921 +
 922 +&vin7 {
 923 +       status = "okay";
 924 +};
 925 +
 926 +&xhci0 {
 927 +       pinctrl-0 = <&usb30_pins>;
 928 +       pinctrl-names = "default";
 929 +
 930 +       status = "okay";
 931 +};
 932 diff --git a/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 933 new file mode 100644
 934 index 000000000000..0a63d2e7a64b
 935 --- /dev/null
 936 +++ b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 937 @@ -0,0 +1,378 @@
 938 +/*
 939 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
 940 + *
 941 + * Copyright (C) 2019 Panasonic Corp.
 942 + * Copyright (C) 2020 Konsulko Group
 943 + *
 944 + * This file is licensed under the terms of the GNU General Public License
 945 + * version 2.  This program is licensed "as is" without any warranty of any
 946 + * kind, whether express or implied.
 947 + */
 948 +
 949 +/*
 950 + * This file is for the most part derived from:
 951 + *
 952 + * - r8a7795-salvator-xs-4x2g.dts
 953 + * - r8a7795-salvator-xs.dts
 954 + * - salvator-xs.dtsi
 955 + *
 956 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
 957 + */
 958 +
 959 +/dts-v1/;
 960 +#include "r8a7795.dtsi"
 961 +#include "agl-refhw-common.dtsi"
 962 +
 963 +/ {
 964 +       model = "AGL Reference Hardware based on r8a7795 ES3.0+ with 8GiB (4 x 2 GiB)";
 965 +       compatible = "agl,refhw-h3", "renesas,r8a7795";
 966 +
 967 +       memory@48000000 {
 968 +               device_type = "memory";
 969 +               /* first 128MB is reserved for secure area. */
 970 +               reg = <0x0 0x48000000 0x0 0x78000000>;
 971 +       };
 972 +
 973 +       memory@500000000 {
 974 +               device_type = "memory";
 975 +               reg = <0x5 0x00000000 0x0 0x80000000>;
 976 +       };
 977 +
 978 +       memory@600000000 {
 979 +               device_type = "memory";
 980 +               reg = <0x6 0x00000000 0x0 0x80000000>;
 981 +       };
 982 +
 983 +       memory@700000000 {
 984 +               device_type = "memory";
 985 +               reg = <0x7 0x00000000 0x0 0x80000000>;
 986 +       };
 987 +
 988 +       reserved-memory {
 989 +               #address-cells = <2>;
 990 +               #size-cells = <2>;
 991 +               ranges;
 992 +
 993 +               /* device specific region for Lossy Decompression */
 994 +               lossy_decompress: linux,lossy_decompress@54000000 {
 995 +                       no-map;
 996 +                       reg = <0x00000000 0x54000000 0x0 0x03000000>;
 997 +               };
 998 +
 999 +               /* For Audio DSP */
1000 +               adsp_reserved: linux,adsp@57000000 {
1001 +                       compatible = "shared-dma-pool";
1002 +                       reusable;
1003 +                       reg = <0x00000000 0x57000000 0x0 0x01000000>;
1004 +               };
1005 +
1006 +               /* global autoconfigured region for contiguous allocations */
1007 +               linux,cma@58000000 {
1008 +                       compatible = "shared-dma-pool";
1009 +                       reusable;
1010 +                       reg = <0x00000000 0x58000000 0x0 0x18000000>;
1011 +                       linux,cma-default;
1012 +               };
1013 +
1014 +               /* device specific region for contiguous allocations */
1015 +               mmp_reserved: linux,multimedia@70000000 {
1016 +                       compatible = "shared-dma-pool";
1017 +                       reusable;
1018 +                       reg = <0x00000000 0x70000000 0x0 0x10000000>;
1019 +               };
1020 +       };
1021 +
1022 +       mmngr {
1023 +               compatible = "renesas,mmngr";
1024 +               memory-region = <&mmp_reserved>, <&lossy_decompress>;
1025 +       };
1026 +
1027 +       mmngrbuf {
1028 +               compatible = "renesas,mmngrbuf";
1029 +       };
1030 +
1031 +       vspm_if {
1032 +               compatible = "renesas,vspm_if";
1033 +       };
1034 +
1035 +       vga {
1036 +               port {
1037 +                       vga_in: endpoint {
1038 +                               /delete-property/remote-endpoint;
1039 +                       };
1040 +               };
1041 +       };
1042 +
1043 +       vga-encoder {
1044 +               ports {
1045 +                       port@0 {
1046 +                               adv7123_in: endpoint {
1047 +                                       /delete-property/remote-endpoint;
1048 +                               };
1049 +                       };
1050 +
1051 +                       port@1 {
1052 +                               adv7123_out: endpoint {
1053 +                                       /delete-property/remote-endpoint;
1054 +                               };
1055 +                       };
1056 +               };
1057 +       };
1058 +
1059 +};
1060 +
1061 +&adsp {
1062 +       status = "okay";
1063 +       memory-region = <&adsp_reserved>;
1064 +};
1065 +
1066 +&du {
1067 +       clocks = <&cpg CPG_MOD 724>,
1068 +                <&cpg CPG_MOD 723>,
1069 +                <&cpg CPG_MOD 722>,
1070 +                <&cpg CPG_MOD 721>,
1071 +                <&versaclock6 1>,
1072 +                <&x21_clk>,
1073 +                <&x22_clk>,
1074 +                <&versaclock6 2>;
1075 +       clock-names = "du.0", "du.1", "du.2", "du.3",
1076 +                     "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1077 +};
1078 +
1079 +&ehci2 {
1080 +       status = "okay";
1081 +};
1082 +
1083 +&ehci3 {
1084 +       dr_mode = "otg";
1085 +       status = "okay";
1086 +};
1087 +
1088 +&hsusb3 {
1089 +       dr_mode = "otg";
1090 +       status = "okay";
1091 +};
1092 +
1093 +&sound_card {
1094 +       dais = <&rsnd_port0     /* ak4613 */
1095 +               &rsnd_port1     /* HDMI0  */
1096 +               &rsnd_port2>;   /* HDMI1  */
1097 +};
1098 +
1099 +&hdmi0 {
1100 +       status = "okay";
1101 +
1102 +       ports {
1103 +               port@1 {
1104 +                       reg = <1>;
1105 +                       rcar_dw_hdmi0_out: endpoint {
1106 +                               remote-endpoint = <&hdmi0_con>;
1107 +                       };
1108 +               };
1109 +               port@2 {
1110 +                       reg = <2>;
1111 +                       dw_hdmi0_snd_in: endpoint {
1112 +                               remote-endpoint = <&rsnd_endpoint1>;
1113 +                       };
1114 +               };
1115 +       };
1116 +};
1117 +
1118 +&hdmi0_con {
1119 +       remote-endpoint = <&rcar_dw_hdmi0_out>;
1120 +};
1121 +
1122 +&hdmi1 {
1123 +       status = "okay";
1124 +
1125 +       ports {
1126 +               port@1 {
1127 +                       reg = <1>;
1128 +                       rcar_dw_hdmi1_out: endpoint {
1129 +                               remote-endpoint = <&hdmi1_con>;
1130 +                       };
1131 +               };
1132 +               port@2 {
1133 +                       reg = <2>;
1134 +                       dw_hdmi1_snd_in: endpoint {
1135 +                               remote-endpoint = <&rsnd_endpoint2>;
1136 +                       };
1137 +               };
1138 +       };
1139 +};
1140 +
1141 +&hdmi1_con {
1142 +       remote-endpoint = <&rcar_dw_hdmi1_out>;
1143 +};
1144 +
1145 +&ohci2 {
1146 +       status = "okay";
1147 +};
1148 +
1149 +&ohci3 {
1150 +       dr_mode = "otg";
1151 +       status = "okay";
1152 +};
1153 +
1154 +&rcar_sound {
1155 +       ports {
1156 +               /* rsnd_port0 is on salvator-common */
1157 +               rsnd_port1: port@1 {
1158 +                       reg = <1>;
1159 +                       rsnd_endpoint1: endpoint {
1160 +                               remote-endpoint = <&dw_hdmi0_snd_in>;
1161 +
1162 +                               dai-format = "i2s";
1163 +                               bitclock-master = <&rsnd_endpoint1>;
1164 +                               frame-master = <&rsnd_endpoint1>;
1165 +
1166 +                               playback = <&ssi2>;
1167 +                       };
1168 +               };
1169 +               rsnd_port2: port@2 {
1170 +                       reg = <2>;
1171 +                       rsnd_endpoint2: endpoint {
1172 +                               remote-endpoint = <&dw_hdmi1_snd_in>;
1173 +
1174 +                               dai-format = "i2s";
1175 +                               bitclock-master = <&rsnd_endpoint2>;
1176 +                               frame-master = <&rsnd_endpoint2>;
1177 +
1178 +                               playback = <&ssi3>;
1179 +                       };
1180 +               };
1181 +       };
1182 +};
1183 +
1184 +&pfc {
1185 +       usb2_pins: usb2 {
1186 +               groups = "usb2", "usb2_ovc";
1187 +               function = "usb2";
1188 +       };
1189 +
1190 +       /*
1191 +        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1192 +        *   (when SW31 is the default setting on Salvator-XS).
1193 +        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1194 +        *   r8a7795 with Salvator-XS.
1195 +        *   Hence the SW31 setting must be changed like 2) below.
1196 +        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1197 +        *      - Connect GP6_3[01] to ADV7842.
1198 +        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1199 +        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1200 +        *      - Connect GP6_{04,21} to ADV7842.
1201 +        */
1202 +       usb2_ch3_pins: usb2_ch3 {
1203 +               groups = "usb2_ch3";
1204 +               function = "usb2_ch3";
1205 +       };
1206 +};
1207 +
1208 +&usb2_phy2 {
1209 +       pinctrl-0 = <&usb2_pins>;
1210 +       pinctrl-names = "default";
1211 +
1212 +       status = "okay";
1213 +};
1214 +
1215 +&usb2_phy3 {
1216 +       pinctrl-0 = <&usb2_ch3_pins>;
1217 +       pinctrl-names = "default";
1218 +
1219 +       status = "okay";
1220 +};
1221 +
1222 +&vspbc {
1223 +       status = "okay";
1224 +};
1225 +
1226 +&vspbd {
1227 +       status = "okay";
1228 +};
1229 +
1230 +&vspi0 {
1231 +       status = "okay";
1232 +};
1233 +
1234 +&vspi1 {
1235 +       status = "okay";
1236 +};
1237 +
1238 +/* End r8a7795-salvator-xs.dts content */
1239 +
1240 +
1241 +/* Start r8a7795-salvator-xs-4x2g.dts content */
1242 +
1243 +&pciec0 {
1244 +       /* Map all possible DDR as inbound ranges */
1245 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1246 +};
1247 +
1248 +&pciec1 {
1249 +       /* Map all possible DDR as inbound ranges */
1250 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1251 +};
1252 +
1253 +/* End r8a7795-salvator-xs-4x2g.dts content */
1254 +
1255 +
1256 +/* Start salvator-xs.dts content */
1257 +
1258 +&extal_clk {
1259 +       clock-frequency = <16640000>;
1260 +};
1261 +
1262 +&i2c4 {
1263 +       clock-frequency = <400000>;
1264 +
1265 +       versaclock6: clock-generator@6a {
1266 +               compatible = "idt,5p49v6901";
1267 +               reg = <0x6a>;
1268 +               #clock-cells = <1>;
1269 +               clocks = <&x23_clk>;
1270 +               clock-names = "xin";
1271 +       };
1272 +};
1273 +
1274 +/* End salvator-xs.dts content */
1275 +
1276 +
1277 +/* Start reference hardware specific tweaks */
1278 +
1279 +&du {
1280 +       ports {
1281 +               port@0 {
1282 +                       endpoint {
1283 +                               /delete-property/remote-endpoint;
1284 +                       };
1285 +               };
1286 +
1287 +               port@3 {
1288 +                       endpoint {
1289 +                               /delete-property/remote-endpoint;
1290 +                       };
1291 +               };
1292 +       };
1293 +};
1294 +
1295 +&lvds0 {
1296 +       status = "disabled";
1297 +};
1298 +
1299 +&pwm1 {
1300 +       status = "disabled";
1301 +};
1302 +
1303 +&scif_clk {
1304 +       clock-frequency = <0>;
1305 +};
1306 +
1307 +&sdhi0 {
1308 +       /delete-property/ wp-gpios;
1309 +       non-removable;
1310 +};
1311 +
1312 +&sdhi3 {
1313 +       /delete-property/ wp-gpios;
1314 +       non-removable;
1315 +};
1316 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1317 index da8f0621a10b..c2b37f70f711 100644
1318 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1319 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1320 @@ -165,6 +165,21 @@ static int adv748x_i2c_addresses[ADV748X_PAGE_MAX] = {
1321         ADV748X_I2C_TXA,
1322  };
1323
1324 +/* Default addresses for the I2C pages 0x71*/
1325 +static int adv748x_i2c_addresses2[ADV748X_PAGE_MAX] = {
1326 +       ADV748X_I2C_IO2,
1327 +       ADV748X_I2C_DPLL2,
1328 +       ADV748X_I2C_CP2,
1329 +       ADV748X_I2C_HDMI2,
1330 +       ADV748X_I2C_EDID2,
1331 +       ADV748X_I2C_REPEATER2,
1332 +       ADV748X_I2C_INFOFRAME2,
1333 +       ADV748X_I2C_CEC2,
1334 +       ADV748X_I2C_SDP2,
1335 +       ADV748X_I2C_TXB2,
1336 +       ADV748X_I2C_TXA2,
1337 +};
1338 +
1339  static int adv748x_read_check(struct adv748x_state *state,
1340                               int client_page, u8 reg)
1341  {
1342 @@ -238,9 +253,16 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
1343         int ret;
1344
1345         for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1346 -               state->i2c_clients[i] =
1347 -                       adv748x_dummy_client(state, adv748x_i2c_addresses[i],
1348 -                                            ADV748X_IO_SLAVE_ADDR_BASE + i);
1349 +               if((state->client->addr << 1) == 0xe0) {
1350 +                       state->i2c_clients[i] =
1351 +                               adv748x_dummy_client(state, adv748x_i2c_addresses[i],
1352 +                                               ADV748X_IO_SLAVE_ADDR_BASE + i);
1353 +               } else {
1354 +                       state->i2c_clients[i] =
1355 +                               adv748x_dummy_client(state, adv748x_i2c_addresses2[i],
1356 +                                               ADV748X_IO_SLAVE_ADDR_BASE + i);
1357 +               }
1358 +
1359                 if (state->i2c_clients[i] == NULL) {
1360                         adv_err(state, "failed to create i2c client %u\n", i);
1361                         return -ENOMEM;
1362 @@ -508,6 +530,20 @@ static const struct adv748x_reg_value adv748x_set_slave_address[] = {
1363         {ADV748X_PAGE_EOR, 0xff, 0xff}  /* End of register table */
1364  };
1365
1366 +static const struct adv748x_reg_value adv748x_set_slave_address2[] = {
1367 +       {ADV748X_PAGE_IO, 0xf3, ADV748X_I2C_DPLL2 << 1},
1368 +       {ADV748X_PAGE_IO, 0xf4, ADV748X_I2C_CP2 << 1},
1369 +       {ADV748X_PAGE_IO, 0xf5, ADV748X_I2C_HDMI2 << 1},
1370 +       {ADV748X_PAGE_IO, 0xf6, ADV748X_I2C_EDID2 << 1},
1371 +       {ADV748X_PAGE_IO, 0xf7, ADV748X_I2C_REPEATER2 << 1},
1372 +       {ADV748X_PAGE_IO, 0xf8, ADV748X_I2C_INFOFRAME2 << 1},
1373 +       {ADV748X_PAGE_IO, 0xfa, ADV748X_I2C_CEC2 << 1},
1374 +       {ADV748X_PAGE_IO, 0xfb, ADV748X_I2C_SDP2 << 1},
1375 +       {ADV748X_PAGE_IO, 0xfc, ADV748X_I2C_TXB2 << 1},
1376 +       {ADV748X_PAGE_IO, 0xfd, ADV748X_I2C_TXA2 << 1},
1377 +       {ADV748X_PAGE_EOR, 0xff, 0xff}  /* End of register table */
1378 +};
1379 +
1380  /* Supported Formats For Script Below */
1381  /* - 01-29 HDMI to MIPI TxA CSI 4-Lane - RGB888: */
1382  static const struct adv748x_reg_value adv748x_init_txa_4lane[] = {
1383 @@ -683,7 +719,11 @@ static int adv748x_reset(struct adv748x_state *state)
1384         if (ret < 0)
1385                 return ret;
1386
1387 -       ret = adv748x_write_regs(state, adv748x_set_slave_address);
1388 +       if((state->client->addr << 1) == 0xe0) {
1389 +               ret = adv748x_write_regs(state, adv748x_set_slave_address);     //i2c address 0x70
1390 +       } else {
1391 +               ret = adv748x_write_regs(state, adv748x_set_slave_address2);    //i2c address 0x71
1392 +       }
1393         if (ret < 0)
1394                 return ret;
1395
1396 diff --git a/drivers/media/i2c/adv748x/adv748x.h b/drivers/media/i2c/adv748x/adv748x.h
1397 index fb30bfade946..ac50a9e41b08 100644
1398 --- a/drivers/media/i2c/adv748x/adv748x.h
1399 +++ b/drivers/media/i2c/adv748x/adv748x.h
1400 @@ -40,6 +40,18 @@
1401  #define ADV748X_I2C_TXB                        0x48    /* CSI-TXB Map */
1402  #define ADV748X_I2C_TXA                        0x4a    /* CSI-TXA Map */
1403
1404 +#define ADV748X_I2C_IO2                        0x71    /* IO Map */
1405 +#define ADV748X_I2C_DPLL2              0x27    /* DPLL Map */
1406 +#define ADV748X_I2C_CP2                        0x23    /* CP Map */
1407 +#define ADV748X_I2C_HDMI2              0x35    /* HDMI Map */
1408 +#define ADV748X_I2C_EDID2              0x37    /* EDID Map */
1409 +#define ADV748X_I2C_REPEATER2          0x33    /* HDMI RX Repeater Map */
1410 +#define ADV748X_I2C_INFOFRAME2         0x30    /* HDMI RX InfoFrame Map */
1411 +#define ADV748X_I2C_CEC2               0x42    /* CEC Map */
1412 +#define ADV748X_I2C_SDP2               0x78    /* SDP Map */
1413 +#define ADV748X_I2C_TXB2               0x49    /* CSI-TXB Map */
1414 +#define ADV748X_I2C_TXA2               0x4b    /* CSI-TXA Map */
1415 +
1416  enum adv748x_page {
1417         ADV748X_PAGE_IO,
1418         ADV748X_PAGE_DPLL,