meta-agl-refhw-gen3/recipes-kernel/linux/files/0001-add-agl-refhw.patch

   1 Add AGL reference hardware support
   2
   3 Upstream-Status: pending
   4
   5 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
   6 Signed-off-by: Raquel Medina <raquel.medina@konsulko.com>
   7
   8 ---
   9  arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi | 912 ++++++++++++++++++++++
  10  arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts | 378 +++++++++
  11  drivers/media/i2c/adv748x/adv748x-core.c          |  48 +-
  12  drivers/media/i2c/adv748x/adv748x.h               |  12 +
  13  4 files changed, 1346 insertions(+), 4 deletions(-)
  14
  15 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  16 new file mode 100644
  17 index 000000000000..a35cd24b27b9
  18 --- /dev/null
  19 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  20 @@ -0,0 +1,918 @@
  21 +// SPDX-License-Identifier: GPL-2.0
  22 +/*
  23 + * Device Tree Source for common parts of AGL Reference Hardware board variants
  24 + *
  25 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
  26 + * Copyright (C) 2020 Konsulko Group
  27 + */
  28 +
  29 +/*
  30 + * This file is derived from salvator-common.dtsi
  31 + *
  32 + * It is currently unclear if the modifications made are such that they could
  33 + * be done on top of salvator-common.dtsi to allow removing the duplication.
  34 + * It is likely that the common pieces with salvator-common.dtsi would need to
  35 + * be factored out into a new common file, which is perhaps hard to justify.
  36 + */
  37 +
  38 +/*
  39 + * SSI-AK4613
  40 + *
  41 + * This command is required when Playback/Capture
  42 + *
  43 + *     amixer set "DVC Out" 100%
  44 + *     amixer set "DVC In" 100%
  45 + *
  46 + * You can use Mute
  47 + *
  48 + *     amixer set "DVC Out Mute" on
  49 + *     amixer set "DVC In Mute" on
  50 + *
  51 + * You can use Volume Ramp
  52 + *
  53 + *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  54 + *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  55 + *     amixer set "DVC Out Ramp" on
  56 + *     aplay xxx.wav &
  57 + *     amixer set "DVC Out"  80%  // Volume Down
  58 + *     amixer set "DVC Out" 100%  // Volume Up
  59 + */
  60 +
  61 +#include <dt-bindings/gpio/gpio.h>
  62 +
  63 +/ {
  64 +       aliases {
  65 +               serial0 = &scif2;
  66 +               serial1 = &scif1;
  67 +               serial2 = &scif5;
  68 +               serial3 = &hscif1;
  69 +               serial4 = &hscif0;
  70 +               serial5 = &hscif2;
  71 +               ethernet0 = &avb;
  72 +       };
  73 +
  74 +       chosen {
  75 +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  76 +               stdout-path = "serial0:115200n8";
  77 +       };
  78 +
  79 +       audio_clkout: audio-clkout {
  80 +               /*
  81 +                * This is same as <&rcar_sound 0>
  82 +                * but needed to avoid cs2000/rcar_sound probe dead-lock
  83 +                */
  84 +               compatible = "fixed-clock";
  85 +               #clock-cells = <0>;
  86 +               clock-frequency = <12288000>;
  87 +       };
  88 +
  89 +       avb-mch@ec5a0100 {
  90 +               compatible = "renesas,avb-mch-gen3";
  91 +               reg =   <0 0xec5a0100 0 0x100>;  /* ADG_AVB */
  92 +               reg-name = "adg_avb";
  93 +
  94 +               clocks = <&cpg CPG_MOD 922>;
  95 +               clock-names = "adg";
  96 +               resets = <&cpg 922>;
  97 +       };
  98 +
  99 +       hdmi0-in {
 100 +               compatible = "hdmi-connector";
 101 +               label = "HDMI0 IN";
 102 +               type = "a";
 103 +
 104 +               port {
 105 +                       hdmi_in_con: endpoint {
 106 +                               remote-endpoint = <&adv7481_hdmi>;
 107 +                       };
 108 +               };
 109 +       };
 110 +
 111 +       hdmi2-in {
 112 +               compatible = "hdmi-connector";
 113 +               label = "HDMI2 IN";
 114 +               type = "a";
 115 +
 116 +               port {
 117 +                       hdmi_in_con2: endpoint {
 118 +                               remote-endpoint = <&adv7481_hdmi2>;
 119 +                       };
 120 +               };
 121 +       };
 122 +
 123 +       reg_1p8v: regulator0 {
 124 +               compatible = "regulator-fixed";
 125 +               regulator-name = "fixed-1.8V";
 126 +               regulator-min-microvolt = <1800000>;
 127 +               regulator-max-microvolt = <1800000>;
 128 +               regulator-boot-on;
 129 +               regulator-always-on;
 130 +       };
 131 +
 132 +       reg_3p3v: regulator1 {
 133 +               compatible = "regulator-fixed";
 134 +               regulator-name = "fixed-3.3V";
 135 +               regulator-min-microvolt = <3300000>;
 136 +               regulator-max-microvolt = <3300000>;
 137 +               regulator-boot-on;
 138 +               regulator-always-on;
 139 +       };
 140 +
 141 +       reg_12v: regulator2 {
 142 +               compatible = "regulator-fixed";
 143 +               regulator-name = "fixed-12V";
 144 +               regulator-min-microvolt = <12000000>;
 145 +               regulator-max-microvolt = <12000000>;
 146 +               regulator-boot-on;
 147 +               regulator-always-on;
 148 +       };
 149 +
 150 +       sound_card: sound {
 151 +               compatible = "audio-graph-card";
 152 +
 153 +               label = "rcar-sound";
 154 +
 155 +               dais = <&rsnd_port0>;
 156 +       };
 157 +
 158 +       vcc_sdhi0: regulator-vcc-sdhi0 {
 159 +               compatible = "regulator-fixed";
 160 +
 161 +               regulator-name = "SDHI0 Vcc";
 162 +               regulator-min-microvolt = <3300000>;
 163 +               regulator-max-microvolt = <3300000>;
 164 +
 165 +               gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 166 +               enable-active-high;
 167 +       };
 168 +
 169 +       vccq_sdhi0: regulator-vccq-sdhi0 {
 170 +               compatible = "regulator-gpio";
 171 +
 172 +               regulator-name = "SDHI0 VccQ";
 173 +               regulator-min-microvolt = <1800000>;
 174 +               regulator-max-microvolt = <3300000>;
 175 +
 176 +               gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 177 +               gpios-states = <1>;
 178 +               states = <3300000 1
 179 +                         1800000 0>;
 180 +       };
 181 +
 182 +       vcc_sdhi3: regulator-vcc-sdhi3 {
 183 +               compatible = "regulator-fixed";
 184 +
 185 +               regulator-name = "SDHI3 Vcc";
 186 +               regulator-min-microvolt = <3300000>;
 187 +               regulator-max-microvolt = <3300000>;
 188 +
 189 +               gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 190 +               enable-active-high;
 191 +       };
 192 +
 193 +       vccq_sdhi3: regulator-vccq-sdhi3 {
 194 +               compatible = "regulator-gpio";
 195 +
 196 +               regulator-name = "SDHI3 VccQ";
 197 +               regulator-min-microvolt = <1800000>;
 198 +               regulator-max-microvolt = <3300000>;
 199 +
 200 +               gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 201 +               gpios-states = <1>;
 202 +               states = <3300000 1
 203 +                         1800000 0>;
 204 +       };
 205 +
 206 +       hdmi0-out {
 207 +               compatible = "hdmi-connector";
 208 +               label = "HDMI0 OUT";
 209 +               type = "a";
 210 +
 211 +               port {
 212 +                       hdmi0_con: endpoint {
 213 +                       };
 214 +               };
 215 +       };
 216 +
 217 +       hdmi1-out {
 218 +               compatible = "hdmi-connector";
 219 +               label = "HDMI1 OUT";
 220 +               type = "a";
 221 +
 222 +               port {
 223 +                       hdmi1_con: endpoint {
 224 +                       };
 225 +               };
 226 +       };
 227 +
 228 +       x12_clk: x12 {
 229 +               compatible = "fixed-clock";
 230 +               #clock-cells = <0>;
 231 +               clock-frequency = <24576000>;
 232 +       };
 233 +
 234 +       /* External DU dot clocks */
 235 +       x21_clk: x21-clock {
 236 +               compatible = "fixed-clock";
 237 +               #clock-cells = <0>;
 238 +               clock-frequency = <33000000>;
 239 +       };
 240 +
 241 +       x22_clk: x22-clock {
 242 +               compatible = "fixed-clock";
 243 +               #clock-cells = <0>;
 244 +               clock-frequency = <33000000>;
 245 +       };
 246 +
 247 +       x23_clk: x23-clock {
 248 +               compatible = "fixed-clock";
 249 +               #clock-cells = <0>;
 250 +               clock-frequency = <25000000>;
 251 +       };
 252 +};
 253 +
 254 +&a57_0 {
 255 +       cpu-supply = <&dvfs>;
 256 +};
 257 +
 258 +&audio_clk_a {
 259 +       clock-frequency = <22579200>;
 260 +};
 261 +
 262 +&avb {
 263 +       pinctrl-0 = <&avb_pins>;
 264 +       pinctrl-names = "default";
 265 +       phy-handle = <&phy0>;
 266 +       phy-mode = "rgmii-txid";
 267 +       status = "okay";
 268 +
 269 +       phy0: ethernet-phy@0 {
 270 +               rxc-skew-ps = <1500>;
 271 +               reg = <0>;
 272 +               interrupt-parent = <&gpio2>;
 273 +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 274 +               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 275 +       };
 276 +};
 277 +
 278 +&csi40 {
 279 +       status = "okay";
 280 +
 281 +       ports {
 282 +               port@0 {
 283 +                       reg = <0>;
 284 +
 285 +                       csi40_in: endpoint {
 286 +                               clock-lanes = <0>;
 287 +                               data-lanes = <1 2 3 4>;
 288 +                               remote-endpoint = <&adv7481_txa>;
 289 +                       };
 290 +               };
 291 +       };
 292 +};
 293 +
 294 +&csi41 {
 295 +       status = "okay";
 296 +
 297 +       ports {
 298 +               port@0 {
 299 +                       reg = <0>;
 300 +
 301 +                       csi41_in: endpoint {
 302 +                               clock-lanes = <0>;
 303 +                               data-lanes = <1 2 3 4>;
 304 +                               remote-endpoint = <&adv7481_txa2>;
 305 +                       };
 306 +               };
 307 +       };
 308 +};
 309 +
 310 +&du {
 311 +       status = "okay";
 312 +
 313 +};
 314 +
 315 +&ehci0 {
 316 +       dr_mode = "otg";
 317 +       status = "okay";
 318 +};
 319 +
 320 +&ehci1 {
 321 +       status = "okay";
 322 +};
 323 +
 324 +&extalr_clk {
 325 +       clock-frequency = <32768>;
 326 +};
 327 +
 328 +&hscif0 {
 329 +       pinctrl-0 = <&hscif0_pins>;
 330 +       pinctrl-names = "default";
 331 +       uart-has-rtscts;
 332 +
 333 +       status = "okay";
 334 +};
 335 +
 336 +&hscif1 {
 337 +       pinctrl-0 = <&hscif1_pins>;
 338 +       pinctrl-names = "default";
 339 +
 340 +       /* Please use exclusively to the scif1 node */
 341 +       status = "okay";
 342 +};
 343 +
 344 +&hscif2 {
 345 +       pinctrl-0 = <&hscif2_pins>;
 346 +       pinctrl-names = "default";
 347 +
 348 +       status = "okay";
 349 +};
 350 +
 351 +&hsusb {
 352 +       dr_mode = "otg";
 353 +       status = "okay";
 354 +};
 355 +
 356 +&i2c2 {
 357 +       pinctrl-0 = <&i2c2_pins>;
 358 +       pinctrl-names = "default";
 359 +
 360 +       status = "okay";
 361 +
 362 +       clock-frequency = <100000>;
 363 +
 364 +       video-receiver@70 {
 365 +               compatible = "adi,adv7481";
 366 +               reg = <0x70 0x26 0x22 0x34 0x36 0x32
 367 +                      0x31 0x30 0x41 0x79 0x4a 0x48>;
 368 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 369 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 370 +
 371 +               #address-cells = <1>;
 372 +               #size-cells = <0>;
 373 +
 374 +               interrupt-parent = <&gpio0>;
 375 +               interrupt-names = "intrq1", "intrq3";
 376 +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
 377 +                            <5 IRQ_TYPE_LEVEL_LOW>;
 378 +
 379 +               port@8 {
 380 +                       reg = <8>;
 381 +
 382 +                       adv7481_hdmi: endpoint {
 383 +                               remote-endpoint = <&hdmi_in_con>;
 384 +                       };
 385 +               };
 386 +
 387 +               port@a {
 388 +                       reg = <10>;
 389 +
 390 +                       adv7481_txa: endpoint {
 391 +                               clock-lanes = <0>;
 392 +                               data-lanes = <1 2 3 4>;
 393 +                               remote-endpoint = <&csi40_in>;
 394 +                       };
 395 +               };
 396 +
 397 +       };
 398 +
 399 +       video-receiver@71 {
 400 +               compatible = "adi,adv7481";
 401 +               reg = <0x71 0x27 0x23 0x35 0x37 0x33
 402 +                      0x28 0x29 0x42 0x78 0x4b 0x49>;
 403 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 404 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 405 +
 406 +               #address-cells = <1>;
 407 +               #size-cells = <0>;
 408 +
 409 +               interrupt-parent = <&gpio6>;
 410 +               interrupt-names = "intrq1", "intrq3";
 411 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
 412 +                            <1 IRQ_TYPE_LEVEL_LOW>;
 413 +
 414 +               port@8 {
 415 +                       reg = <8>;
 416 +
 417 +                       adv7481_hdmi2: endpoint {
 418 +                               remote-endpoint = <&hdmi_in_con2>;
 419 +                       };
 420 +               };
 421 +
 422 +               port@a {
 423 +                       reg = <10>;
 424 +
 425 +                       adv7481_txa2: endpoint {
 426 +                               clock-lanes = <0>;
 427 +                               data-lanes = <1 2 3 4>;
 428 +                               remote-endpoint = <&csi41_in>;
 429 +                       };
 430 +               };
 431 +       };
 432 +
 433 +       cs2000: clk_multiplier@4f {
 434 +               #clock-cells = <0>;
 435 +               compatible = "cirrus,cs2000-cp";
 436 +               reg = <0x4f>;
 437 +               clocks = <&audio_clkout>, <&x12_clk>;
 438 +               clock-names = "clk_in", "ref_clk";
 439 +
 440 +               assigned-clocks = <&cs2000>;
 441 +               assigned-clock-rates = <24576000>; /* 1/1 divide */
 442 +       };
 443 +};
 444 +
 445 +&i2c3 {
 446 +       pinctrl-0 = <&i2c3_pins>;
 447 +       pinctrl-names = "default";
 448 +
 449 +       status = "okay";
 450 +
 451 +       clock-frequency = <100000>;
 452 +
 453 +       asm330lhh@6a {
 454 +               compatible = "st,asm330lhh";
 455 +               reg = <0x6a>;
 456 +
 457 +               interrupt-names = "int1", "int2";
 458 +               interrupts = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
 459 +                            <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
 460 +       };
 461 +};
 462 +
 463 +&i2c4 {
 464 +       status = "okay";
 465 +
 466 +       versaclock5: clock-generator@68 {
 467 +               compatible = "idt,9fgv0841";
 468 +               reg = <0x68>;
 469 +               #clock-cells = <1>;
 470 +               clocks = <&x23_clk>;
 471 +               clock-names = "xin";
 472 +       };
 473 +};
 474 +
 475 +&i2c5 {
 476 +       pinctrl-0 = <&i2c5_pins>;
 477 +       pinctrl-names = "default";
 478 +
 479 +       status = "okay";
 480 +
 481 +       clock-frequency = <100000>;
 482 +
 483 +       ak4613: codec@10 {
 484 +               compatible = "asahi-kasei,ak4613";
 485 +               #sound-dai-cells = <0>;
 486 +               reg = <0x10>;
 487 +               clocks = <&rcar_sound 3>;
 488 +
 489 +               asahi-kasei,in1-single-end;
 490 +               asahi-kasei,in2-single-end;
 491 +               asahi-kasei,out1-single-end;
 492 +               asahi-kasei,out2-single-end;
 493 +               asahi-kasei,out3-single-end;
 494 +               asahi-kasei,out4-single-end;
 495 +               asahi-kasei,out5-single-end;
 496 +               asahi-kasei,out6-single-end;
 497 +
 498 +               port {
 499 +                       ak4613_endpoint: endpoint {
 500 +                               remote-endpoint = <&rsnd_endpoint0>;
 501 +                       };
 502 +               };
 503 +       };
 504 +};
 505 +
 506 +&i2c_dvfs {
 507 +       status = "okay";
 508 +
 509 +       clock-frequency = <400000>;
 510 +
 511 +       pmic: pmic@30 {
 512 +               pinctrl-0 = <&irq0_pins>;
 513 +               pinctrl-names = "default";
 514 +
 515 +               compatible = "rohm,bd9571mwv";
 516 +               reg = <0x30>;
 517 +               interrupt-parent = <&intc_ex>;
 518 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 519 +               interrupt-controller;
 520 +               #interrupt-cells = <2>;
 521 +               gpio-controller;
 522 +               #gpio-cells = <2>;
 523 +               rohm,ddr-backup-power = <0xf>;
 524 +               rohm,rstbmode-level;
 525 +
 526 +               regulators {
 527 +                       dvfs: dvfs {
 528 +                               regulator-name = "dvfs";
 529 +                               regulator-min-microvolt = <750000>;
 530 +                               regulator-max-microvolt = <1030000>;
 531 +                               regulator-boot-on;
 532 +                               regulator-always-on;
 533 +                       };
 534 +               };
 535 +       };
 536 +
 537 +       eeprom@50 {
 538 +               compatible = "rohm,br24t01", "atmel,24c01";
 539 +               reg = <0x50>;
 540 +               pagesize = <8>;
 541 +       };
 542 +};
 543 +
 544 +&ohci0 {
 545 +       dr_mode = "otg";
 546 +       status = "okay";
 547 +};
 548 +
 549 +&ohci1 {
 550 +       status = "okay";
 551 +};
 552 +
 553 +&pcie_bus_clk {
 554 +       clock-frequency = <100000000>;
 555 +       status = "okay";
 556 +};
 557 +
 558 +&pciec0 {
 559 +       status = "okay";
 560 +};
 561 +
 562 +&pciec1 {
 563 +       status = "okay";
 564 +};
 565 +
 566 +&canfd {
 567 +       pinctrl-0 = <&canfd0_pins &canfd1_pins>;
 568 +       pinctrl-names = "default";
 569 +
 570 +       status = "okay";
 571 +
 572 +       channel0 {
 573 +               status = "okay";
 574 +       };
 575 +
 576 +       channel1 {
 577 +               status = "okay";
 578 +       };
 579 +};
 580 +
 581 +&pfc {
 582 +       pinctrl-0 = <&scif_clk_pins>;
 583 +       pinctrl-names = "default";
 584 +
 585 +       avb_pins: avb {
 586 +               mux {
 587 +                       groups = "avb_link", "avb_mdio", "avb_mii";
 588 +                       function = "avb";
 589 +               };
 590 +
 591 +               pins_mdio {
 592 +                       groups = "avb_mdio";
 593 +                       drive-strength = <24>;
 594 +               };
 595 +
 596 +               pins_mii_tx {
 597 +                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 598 +                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 599 +                       drive-strength = <12>;
 600 +               };
 601 +       };
 602 +
 603 +       hscif0_pins: hscif0 {
 604 +               groups = "hscif0_data", "hscif0_ctrl";
 605 +               function = "hscif0";
 606 +       };
 607 +
 608 +       hscif1_pins: hscif1 {
 609 +               groups = "hscif1_data_a";
 610 +               function = "hscif1";
 611 +       };
 612 +
 613 +       hscif2_pins: hscif2 {
 614 +               groups = "hscif2_data_c";
 615 +               function = "hscif2";
 616 +       };
 617 +
 618 +       i2c2_pins: i2c2 {
 619 +               groups = "i2c2_a";
 620 +               function = "i2c2";
 621 +       };
 622 +
 623 +       i2c3_pins: i2c3 {
 624 +               groups = "i2c3";
 625 +               function = "i2c3";
 626 +       };
 627 +
 628 +       i2c5_pins: i2c5 {
 629 +               groups = "i2c5";
 630 +               function = "i2c5";
 631 +       };
 632 +
 633 +       irq0_pins: irq0 {
 634 +               groups = "intc_ex_irq0";
 635 +               function = "intc_ex";
 636 +       };
 637 +
 638 +       scif1_pins: scif1 {
 639 +               groups = "scif1_data_b";
 640 +               function = "scif1";
 641 +       };
 642 +
 643 +       scif2_pins: scif2 {
 644 +               groups = "scif2_data_a";
 645 +               function = "scif2";
 646 +       };
 647 +
 648 +       scif5_pins: scif5 {
 649 +               groups = "scif5_data_a";
 650 +               function = "scif5";
 651 +       };
 652 +
 653 +       scif_clk_pins: scif_clk {
 654 +               groups = "scif_clk_a";
 655 +               function = "scif_clk";
 656 +       };
 657 +
 658 +       sdhi0_pins: sd0 {
 659 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 660 +               function = "sdhi0";
 661 +               power-source = <3300>;
 662 +       };
 663 +
 664 +       sdhi0_pins_uhs: sd0_uhs {
 665 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 666 +               function = "sdhi0";
 667 +               power-source = <1800>;
 668 +       };
 669 +
 670 +       sdhi2_pins: sd2 {
 671 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 672 +               function = "sdhi2";
 673 +               power-source = <3300>;
 674 +       };
 675 +
 676 +       sdhi2_pins_uhs: sd2_uhs {
 677 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 678 +               function = "sdhi2";
 679 +               power-source = <1800>;
 680 +       };
 681 +
 682 +       sdhi3_pins: sd3 {
 683 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 684 +               function = "sdhi3";
 685 +               power-source = <3300>;
 686 +       };
 687 +
 688 +       sdhi3_pins_uhs: sd3_uhs {
 689 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 690 +               function = "sdhi3";
 691 +               power-source = <1800>;
 692 +       };
 693 +
 694 +       sound_pins: sound {
 695 +               groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
 696 +               function = "ssi";
 697 +       };
 698 +
 699 +       sound_clk_pins: sound_clk {
 700 +               groups = "audio_clk_a_a", "audio_clk_b_a",
 701 +                        "audio_clkout_a", "audio_clkout3_b";
 702 +               function = "audio_clk";
 703 +       };
 704 +
 705 +       usb0_pins: usb0 {
 706 +               groups = "usb0";
 707 +               function = "usb0";
 708 +       };
 709 +
 710 +       usb1_pins: usb1 {
 711 +               groups = "usb1";
 712 +               function = "usb1";
 713 +       };
 714 +
 715 +       usb30_pins: usb30 {
 716 +               groups = "usb30", "usb30_ovc";
 717 +               function = "usb30";
 718 +       };
 719 +
 720 +       canfd0_pins: canfd0 {
 721 +               groups = "canfd0_data_a";
 722 +               function = "canfd0";
 723 +       };
 724 +
 725 +       canfd1_pins: canfd1 {
 726 +               groups = "canfd1_data";
 727 +               function = "canfd1";
 728 +       };
 729 +};
 730 +
 731 +&rcar_sound {
 732 +       pinctrl-0 = <&sound_pins &sound_clk_pins>;
 733 +       pinctrl-names = "default";
 734 +
 735 +       /* Single DAI */
 736 +       #sound-dai-cells = <0>;
 737 +
 738 +       /* audio_clkout0/1/2/3 */
 739 +       #clock-cells = <1>;
 740 +       clock-frequency = <12288000 11289600>;
 741 +
 742 +       status = "okay";
 743 +
 744 +       /* update <audio_clk_b> to <cs2000> */
 745 +       clocks = <&cpg CPG_MOD 1005>,
 746 +                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 747 +                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 748 +                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 749 +                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 750 +                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 751 +                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 752 +                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 753 +                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 754 +                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 755 +                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 756 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 757 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 758 +                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 759 +                <&audio_clk_a>, <&cs2000>,
 760 +                <&audio_clk_c>,
 761 +                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
 762 +
 763 +       ports {
 764 +               #address-cells = <1>;
 765 +               #size-cells = <0>;
 766 +               rsnd_port0: port@0 {
 767 +                       reg = <0>;
 768 +                       rsnd_endpoint0: endpoint {
 769 +                               remote-endpoint = <&ak4613_endpoint>;
 770 +
 771 +                               dai-format = "left_j";
 772 +                               bitclock-master = <&rsnd_endpoint0>;
 773 +                               frame-master = <&rsnd_endpoint0>;
 774 +
 775 +                               playback = <&ssi3>; //ssi0 -> ssi3
 776 +                               capture  = <&ssi4>; //ssi1 -> ssi4
 777 +                       };
 778 +               };
 779 +       };
 780 +};
 781 +
 782 +&rwdt {
 783 +       timeout-sec = <60>;
 784 +       status = "okay";
 785 +};
 786 +
 787 +&scif1 {
 788 +       pinctrl-0 = <&scif1_pins>;
 789 +       pinctrl-names = "default";
 790 +
 791 +       uart-has-rtscts;
 792 +       /* Please use exclusively to the hscif1 node */
 793 +       status = "okay";
 794 +};
 795 +
 796 +&scif2 {
 797 +       pinctrl-0 = <&scif2_pins>;
 798 +       pinctrl-names = "default";
 799 +
 800 +       status = "okay";
 801 +};
 802 +
 803 +&scif5 {
 804 +       pinctrl-0 = <&scif5_pins>;
 805 +       pinctrl-names = "default";
 806 +
 807 +       status = "okay";
 808 +};
 809 +
 810 +&scif_clk {
 811 +       clock-frequency = <14745600>;
 812 +};
 813 +
 814 +&sdhi0 {
 815 +       pinctrl-0 = <&sdhi0_pins>;
 816 +       pinctrl-1 = <&sdhi0_pins_uhs>;
 817 +       pinctrl-names = "default", "state_uhs";
 818 +
 819 +       vmmc-supply = <&vcc_sdhi0>;
 820 +       vqmmc-supply = <&vccq_sdhi0>;
 821 +       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 822 +       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 823 +       bus-width = <4>;
 824 +       sd-uhs-sdr50;
 825 +       sd-uhs-sdr104;
 826 +       status = "okay";
 827 +};
 828 +
 829 +&sdhi2 {
 830 +       /* used for on-board 8bit eMMC */
 831 +       pinctrl-0 = <&sdhi2_pins>;
 832 +       pinctrl-1 = <&sdhi2_pins_uhs>;
 833 +       pinctrl-names = "default", "state_uhs";
 834 +
 835 +       iommus = <&ipmmu_ds1 34>;
 836 +
 837 +       vmmc-supply = <&reg_3p3v>;
 838 +       vqmmc-supply = <&reg_1p8v>;
 839 +       bus-width = <8>;
 840 +       mmc-hs200-1_8v;
 841 +       mmc-hs400-1_8v;
 842 +       no-sd;
 843 +       no-sdio;
 844 +       non-removable;
 845 +       fixed-emmc-driver-type = <1>;
 846 +       status = "okay";
 847 +};
 848 +
 849 +&sdhi3 {
 850 +       pinctrl-0 = <&sdhi3_pins>;
 851 +       pinctrl-1 = <&sdhi3_pins_uhs>;
 852 +       pinctrl-names = "default", "state_uhs";
 853 +
 854 +       vmmc-supply = <&vcc_sdhi3>;
 855 +       vqmmc-supply = <&vccq_sdhi3>;
 856 +       cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 857 +       wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 858 +       bus-width = <4>;
 859 +       sd-uhs-sdr50;
 860 +       sd-uhs-sdr104;
 861 +       status = "okay";
 862 +};
 863 +
 864 +&ssi4 {
 865 +       shared-pin;
 866 +};
 867 +
 868 +&usb_extal_clk {
 869 +       clock-frequency = <50000000>;
 870 +};
 871 +
 872 +&usb2_phy0 {
 873 +       pinctrl-0 = <&usb0_pins>;
 874 +       pinctrl-names = "default";
 875 +
 876 +       status = "okay";
 877 +};
 878 +
 879 +&usb2_phy1 {
 880 +       pinctrl-0 = <&usb1_pins>;
 881 +       pinctrl-names = "default";
 882 +
 883 +       status = "okay";
 884 +};
 885 +
 886 +&usb3_peri0 {
 887 +       phys = <&usb3_phy0>;
 888 +       phy-names = "usb";
 889 +
 890 +       status = "okay";
 891 +};
 892 +
 893 +&usb3_phy0 {
 894 +       status = "okay";
 895 +};
 896 +
 897 +&usb3s0_clk {
 898 +       clock-frequency = <100000000>;
 899 +};
 900 +
 901 +&vin0 {
 902 +       status = "okay";
 903 +};
 904 +
 905 +&vin1 {
 906 +       status = "okay";
 907 +};
 908 +
 909 +&vin2 {
 910 +       status = "okay";
 911 +};
 912 +
 913 +&vin3 {
 914 +       status = "okay";
 915 +};
 916 +
 917 +&vin4 {
 918 +       status = "okay";
 919 +};
 920 +
 921 +&vin5 {
 922 +       status = "okay";
 923 +};
 924 +
 925 +&vin6 {
 926 +       status = "okay";
 927 +};
 928 +
 929 +&vin7 {
 930 +       status = "okay";
 931 +};
 932 +
 933 +&xhci0 {
 934 +       pinctrl-0 = <&usb30_pins>;
 935 +       pinctrl-names = "default";
 936 +
 937 +       status = "okay";
 938 +};
 939 diff --git a/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 940 new file mode 100644
 941 index 000000000000..0a63d2e7a64b
 942 --- /dev/null
 943 +++ b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 944 @@ -0,0 +1,378 @@
 945 +/*
 946 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
 947 + *
 948 + * Copyright (C) 2019 Panasonic Corp.
 949 + * Copyright (C) 2020 Konsulko Group
 950 + *
 951 + * This file is licensed under the terms of the GNU General Public License
 952 + * version 2.  This program is licensed "as is" without any warranty of any
 953 + * kind, whether express or implied.
 954 + */
 955 +
 956 +/*
 957 + * This file is for the most part derived from:
 958 + *
 959 + * - r8a7795-salvator-xs-4x2g.dts
 960 + * - r8a7795-salvator-xs.dts
 961 + * - salvator-xs.dtsi
 962 + *
 963 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
 964 + */
 965 +
 966 +/dts-v1/;
 967 +#include "r8a7795.dtsi"
 968 +#include "agl-refhw-common.dtsi"
 969 +
 970 +/ {
 971 +       model = "AGL Reference Hardware based on r8a7795 ES3.0+ with 8GiB (4 x 2 GiB)";
 972 +       compatible = "agl,refhw-h3", "renesas,r8a7795";
 973 +
 974 +       memory@48000000 {
 975 +               device_type = "memory";
 976 +               /* first 128MB is reserved for secure area. */
 977 +               reg = <0x0 0x48000000 0x0 0x78000000>;
 978 +       };
 979 +
 980 +       memory@500000000 {
 981 +               device_type = "memory";
 982 +               reg = <0x5 0x00000000 0x0 0x80000000>;
 983 +       };
 984 +
 985 +       memory@600000000 {
 986 +               device_type = "memory";
 987 +               reg = <0x6 0x00000000 0x0 0x80000000>;
 988 +       };
 989 +
 990 +       memory@700000000 {
 991 +               device_type = "memory";
 992 +               reg = <0x7 0x00000000 0x0 0x80000000>;
 993 +       };
 994 +
 995 +       reserved-memory {
 996 +               #address-cells = <2>;
 997 +               #size-cells = <2>;
 998 +               ranges;
 999 +
1000 +               /* device specific region for Lossy Decompression */
1001 +               lossy_decompress: linux,lossy_decompress@54000000 {
1002 +                       no-map;
1003 +                       reg = <0x00000000 0x54000000 0x0 0x03000000>;
1004 +               };
1005 +
1006 +               /* For Audio DSP */
1007 +               adsp_reserved: linux,adsp@57000000 {
1008 +                       compatible = "shared-dma-pool";
1009 +                       reusable;
1010 +                       reg = <0x00000000 0x57000000 0x0 0x01000000>;
1011 +               };
1012 +
1013 +               /* global autoconfigured region for contiguous allocations */
1014 +               linux,cma@58000000 {
1015 +                       compatible = "shared-dma-pool";
1016 +                       reusable;
1017 +                       reg = <0x00000000 0x58000000 0x0 0x18000000>;
1018 +                       linux,cma-default;
1019 +               };
1020 +
1021 +               /* device specific region for contiguous allocations */
1022 +               mmp_reserved: linux,multimedia@70000000 {
1023 +                       compatible = "shared-dma-pool";
1024 +                       reusable;
1025 +                       reg = <0x00000000 0x70000000 0x0 0x10000000>;
1026 +               };
1027 +       };
1028 +
1029 +       mmngr {
1030 +               compatible = "renesas,mmngr";
1031 +               memory-region = <&mmp_reserved>, <&lossy_decompress>;
1032 +       };
1033 +
1034 +       mmngrbuf {
1035 +               compatible = "renesas,mmngrbuf";
1036 +       };
1037 +
1038 +       vspm_if {
1039 +               compatible = "renesas,vspm_if";
1040 +       };
1041 +
1042 +       vga {
1043 +               port {
1044 +                       vga_in: endpoint {
1045 +                               /delete-property/remote-endpoint;
1046 +                       };
1047 +               };
1048 +       };
1049 +
1050 +       vga-encoder {
1051 +               ports {
1052 +                       port@0 {
1053 +                               adv7123_in: endpoint {
1054 +                                       /delete-property/remote-endpoint;
1055 +                               };
1056 +                       };
1057 +
1058 +                       port@1 {
1059 +                               adv7123_out: endpoint {
1060 +                                       /delete-property/remote-endpoint;
1061 +                               };
1062 +                       };
1063 +               };
1064 +       };
1065 +
1066 +};
1067 +
1068 +&adsp {
1069 +       status = "okay";
1070 +       memory-region = <&adsp_reserved>;
1071 +};
1072 +
1073 +&du {
1074 +       clocks = <&cpg CPG_MOD 724>,
1075 +                <&cpg CPG_MOD 723>,
1076 +                <&cpg CPG_MOD 722>,
1077 +                <&cpg CPG_MOD 721>,
1078 +                <&versaclock6 1>,
1079 +                <&x21_clk>,
1080 +                <&x22_clk>,
1081 +                <&versaclock6 2>;
1082 +       clock-names = "du.0", "du.1", "du.2", "du.3",
1083 +                     "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1084 +};
1085 +
1086 +&ehci2 {
1087 +       status = "okay";
1088 +};
1089 +
1090 +&ehci3 {
1091 +       dr_mode = "otg";
1092 +       status = "okay";
1093 +};
1094 +
1095 +&hsusb3 {
1096 +       dr_mode = "otg";
1097 +       status = "okay";
1098 +};
1099 +
1100 +&sound_card {
1101 +       dais = <&rsnd_port0     /* ak4613 */
1102 +               &rsnd_port1     /* HDMI0  */
1103 +               &rsnd_port2>;   /* HDMI1  */
1104 +};
1105 +
1106 +&hdmi0 {
1107 +       status = "okay";
1108 +
1109 +       ports {
1110 +               port@1 {
1111 +                       reg = <1>;
1112 +                       rcar_dw_hdmi0_out: endpoint {
1113 +                               remote-endpoint = <&hdmi0_con>;
1114 +                       };
1115 +               };
1116 +               port@2 {
1117 +                       reg = <2>;
1118 +                       dw_hdmi0_snd_in: endpoint {
1119 +                               remote-endpoint = <&rsnd_endpoint1>;
1120 +                       };
1121 +               };
1122 +       };
1123 +};
1124 +
1125 +&hdmi0_con {
1126 +       remote-endpoint = <&rcar_dw_hdmi0_out>;
1127 +};
1128 +
1129 +&hdmi1 {
1130 +       status = "okay";
1131 +
1132 +       ports {
1133 +               port@1 {
1134 +                       reg = <1>;
1135 +                       rcar_dw_hdmi1_out: endpoint {
1136 +                               remote-endpoint = <&hdmi1_con>;
1137 +                       };
1138 +               };
1139 +               port@2 {
1140 +                       reg = <2>;
1141 +                       dw_hdmi1_snd_in: endpoint {
1142 +                               remote-endpoint = <&rsnd_endpoint2>;
1143 +                       };
1144 +               };
1145 +       };
1146 +};
1147 +
1148 +&hdmi1_con {
1149 +       remote-endpoint = <&rcar_dw_hdmi1_out>;
1150 +};
1151 +
1152 +&ohci2 {
1153 +       status = "okay";
1154 +};
1155 +
1156 +&ohci3 {
1157 +       dr_mode = "otg";
1158 +       status = "okay";
1159 +};
1160 +
1161 +&rcar_sound {
1162 +       ports {
1163 +               /* rsnd_port0 is on salvator-common */
1164 +               rsnd_port1: port@1 {
1165 +                       reg = <1>;
1166 +                       rsnd_endpoint1: endpoint {
1167 +                               remote-endpoint = <&dw_hdmi0_snd_in>;
1168 +
1169 +                               dai-format = "i2s";
1170 +                               bitclock-master = <&rsnd_endpoint1>;
1171 +                               frame-master = <&rsnd_endpoint1>;
1172 +
1173 +                               playback = <&ssi2>;
1174 +                       };
1175 +               };
1176 +               rsnd_port2: port@2 {
1177 +                       reg = <2>;
1178 +                       rsnd_endpoint2: endpoint {
1179 +                               remote-endpoint = <&dw_hdmi1_snd_in>;
1180 +
1181 +                               dai-format = "i2s";
1182 +                               bitclock-master = <&rsnd_endpoint2>;
1183 +                               frame-master = <&rsnd_endpoint2>;
1184 +
1185 +                               playback = <&ssi3>;
1186 +                       };
1187 +               };
1188 +       };
1189 +};
1190 +
1191 +&pfc {
1192 +       usb2_pins: usb2 {
1193 +               groups = "usb2", "usb2_ovc";
1194 +               function = "usb2";
1195 +       };
1196 +
1197 +       /*
1198 +        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1199 +        *   (when SW31 is the default setting on Salvator-XS).
1200 +        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1201 +        *   r8a7795 with Salvator-XS.
1202 +        *   Hence the SW31 setting must be changed like 2) below.
1203 +        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1204 +        *      - Connect GP6_3[01] to ADV7842.
1205 +        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1206 +        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1207 +        *      - Connect GP6_{04,21} to ADV7842.
1208 +        */
1209 +       usb2_ch3_pins: usb2_ch3 {
1210 +               groups = "usb2_ch3";
1211 +               function = "usb2_ch3";
1212 +       };
1213 +};
1214 +
1215 +&usb2_phy2 {
1216 +       pinctrl-0 = <&usb2_pins>;
1217 +       pinctrl-names = "default";
1218 +
1219 +       status = "okay";
1220 +};
1221 +
1222 +&usb2_phy3 {
1223 +       pinctrl-0 = <&usb2_ch3_pins>;
1224 +       pinctrl-names = "default";
1225 +
1226 +       status = "okay";
1227 +};
1228 +
1229 +&vspbc {
1230 +       status = "okay";
1231 +};
1232 +
1233 +&vspbd {
1234 +       status = "okay";
1235 +};
1236 +
1237 +&vspi0 {
1238 +       status = "okay";
1239 +};
1240 +
1241 +&vspi1 {
1242 +       status = "okay";
1243 +};
1244 +
1245 +/* End r8a7795-salvator-xs.dts content */
1246 +
1247 +
1248 +/* Start r8a7795-salvator-xs-4x2g.dts content */
1249 +
1250 +&pciec0 {
1251 +       /* Map all possible DDR as inbound ranges */
1252 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1253 +};
1254 +
1255 +&pciec1 {
1256 +       /* Map all possible DDR as inbound ranges */
1257 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1258 +};
1259 +
1260 +/* End r8a7795-salvator-xs-4x2g.dts content */
1261 +
1262 +
1263 +/* Start salvator-xs.dts content */
1264 +
1265 +&extal_clk {
1266 +       clock-frequency = <16640000>;
1267 +};
1268 +
1269 +&i2c4 {
1270 +       clock-frequency = <400000>;
1271 +
1272 +       versaclock6: clock-generator@6a {
1273 +               compatible = "idt,5p49v6901";
1274 +               reg = <0x6a>;
1275 +               #clock-cells = <1>;
1276 +               clocks = <&x23_clk>;
1277 +               clock-names = "xin";
1278 +       };
1279 +};
1280 +
1281 +/* End salvator-xs.dts content */
1282 +
1283 +
1284 +/* Start reference hardware specific tweaks */
1285 +
1286 +&du {
1287 +       ports {
1288 +               port@0 {
1289 +                       endpoint {
1290 +                               /delete-property/remote-endpoint;
1291 +                       };
1292 +               };
1293 +
1294 +               port@3 {
1295 +                       endpoint {
1296 +                               /delete-property/remote-endpoint;
1297 +                       };
1298 +               };
1299 +       };
1300 +};
1301 +
1302 +&lvds0 {
1303 +       status = "disabled";
1304 +};
1305 +
1306 +&pwm1 {
1307 +       status = "disabled";
1308 +};
1309 +
1310 +&scif_clk {
1311 +       clock-frequency = <0>;
1312 +};
1313 +
1314 +&sdhi0 {
1315 +       /delete-property/ wp-gpios;
1316 +       non-removable;
1317 +};
1318 +
1319 +&sdhi3 {
1320 +       /delete-property/ wp-gpios;
1321 +       non-removable;
1322 +};
1323 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1324 index da8f0621a10b..c2b37f70f711 100644
1325 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1326 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1327 @@ -97,6 +97,21 @@ static const struct adv748x_register_map
1328         [ADV748X_PAGE_TXA] = { "txa", 0x4a },
1329  };
1330
1331 +static const struct adv748x_register_map adv748x_default_addresses2[] = {
1332 +       [ADV748X_PAGE_IO] = { "main", 0x71 },
1333 +       [ADV748X_PAGE_DPLL] = { "dpll", 0x27 },
1334 +       [ADV748X_PAGE_CP] = { "cp", 0x23 },
1335 +       [ADV748X_PAGE_HDMI] = { "hdmi", 0x35 },
1336 +       [ADV748X_PAGE_EDID] = { "edid", 0x37 },
1337 +       [ADV748X_PAGE_REPEATER] = { "repeater", 0x33 },
1338 +       [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x28 },
1339 +       [ADV748X_PAGE_CBUS] = { "cbus", 0x29 },
1340 +       [ADV748X_PAGE_CEC] = { "cec", 0x42 },
1341 +       [ADV748X_PAGE_SDP] = { "sdp", 0x78 },
1342 +       [ADV748X_PAGE_TXB] = { "txb", 0x49 },
1343 +       [ADV748X_PAGE_TXA] = { "txa", 0x4b },
1344 +};
1345 +
1346  static int adv748x_read_check(struct adv748x_state *state,
1347                               int client_page, u8 reg)
1348  {
1349 @@ -183,10 +198,17 @@ static int adv748x_initialise_clients(st
1350         int ret;
1351
1352         for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1353 -               state->i2c_clients[i] = i2c_new_ancillary_device(
1354 +               if ((state->client->addr << 1) == 0xe0) {
1355 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1356                                 state->client,
1357                                 adv748x_default_addresses[i].name,
1358                                 adv748x_default_addresses[i].default_addr);
1359 +               } else {
1360 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1361 +                               state->client,
1362 +                               adv748x_default_addresses2[i].name,
1363 +                               adv748x_default_addresses2[i].default_addr);
1364 +               }
1365
1366                 if (IS_ERR(state->i2c_clients[i])) {
1367                         adv_err(state, "failed to create i2c client %u\n", i);
1368
1369