meta-agl-refhw-gen3/recipes-kernel/linux/files/0001-add-agl-refhw.patch

   1 Add AGL reference hardware support
   2
   3 Upstream-Status: pending
   4
   5 Signed-off-by: Scott Murray <scott.murray@konsulko.com>
   6 Signed-off-by: Raquel Medina <raquel.medina@konsulko.com>
   7
   8 ---
   9  arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi | 918 ++++++++++++++++++++++
  10  arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts | 378 +++++++++
  11  drivers/media/i2c/adv748x/adv748x-core.c          |  24 +-
  12  3 files changed, 1319 insertions(+), 1 deletion(-)
  13
  14 diff --git a/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  15 new file mode 100644
  16 index 000000000000..cdd5975a77a2
  17 --- /dev/null
  18 +++ b/arch/arm64/boot/dts/renesas/agl-refhw-common.dtsi
  19 @@ -0,0 +1,918 @@
  20 +// SPDX-License-Identifier: GPL-2.0
  21 +/*
  22 + * Device Tree Source for common parts of AGL Reference Hardware board variants
  23 + *
  24 + * Copyright (C) 2015-2017 Renesas Electronics Corp.
  25 + * Copyright (C) 2020 Konsulko Group
  26 + */
  27 +
  28 +/*
  29 + * This file is derived from salvator-common.dtsi
  30 + *
  31 + * It is currently unclear if the modifications made are such that they could
  32 + * be done on top of salvator-common.dtsi to allow removing the duplication.
  33 + * It is likely that the common pieces with salvator-common.dtsi would need to
  34 + * be factored out into a new common file, which is perhaps hard to justify.
  35 + */
  36 +
  37 +/*
  38 + * SSI-AK4613
  39 + *
  40 + * This command is required when Playback/Capture
  41 + *
  42 + *     amixer set "DVC Out" 100%
  43 + *     amixer set "DVC In" 100%
  44 + *
  45 + * You can use Mute
  46 + *
  47 + *     amixer set "DVC Out Mute" on
  48 + *     amixer set "DVC In Mute" on
  49 + *
  50 + * You can use Volume Ramp
  51 + *
  52 + *     amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  53 + *     amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  54 + *     amixer set "DVC Out Ramp" on
  55 + *     aplay xxx.wav &
  56 + *     amixer set "DVC Out"  80%  // Volume Down
  57 + *     amixer set "DVC Out" 100%  // Volume Up
  58 + */
  59 +
  60 +#include <dt-bindings/gpio/gpio.h>
  61 +
  62 +/ {
  63 +       aliases {
  64 +               serial0 = &scif2;
  65 +               serial1 = &scif1;
  66 +               serial2 = &scif5;
  67 +               serial3 = &hscif1;
  68 +               serial4 = &hscif0;
  69 +               serial5 = &hscif2;
  70 +               ethernet0 = &avb;
  71 +       };
  72 +
  73 +       chosen {
  74 +               bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  75 +               stdout-path = "serial0:115200n8";
  76 +       };
  77 +
  78 +       audio_clkout: audio-clkout {
  79 +               /*
  80 +                * This is same as <&rcar_sound 0>
  81 +                * but needed to avoid cs2000/rcar_sound probe dead-lock
  82 +                */
  83 +               compatible = "fixed-clock";
  84 +               #clock-cells = <0>;
  85 +               clock-frequency = <12288000>;
  86 +       };
  87 +
  88 +       avb-mch@ec5a0100 {
  89 +               compatible = "renesas,avb-mch-gen3";
  90 +               reg =   <0 0xec5a0100 0 0x100>;  /* ADG_AVB */
  91 +               reg-name = "adg_avb";
  92 +
  93 +               clocks = <&cpg CPG_MOD 922>;
  94 +               clock-names = "adg";
  95 +               resets = <&cpg 922>;
  96 +       };
  97 +
  98 +       hdmi0-in {
  99 +               compatible = "hdmi-connector";
 100 +               label = "HDMI0 IN";
 101 +               type = "a";
 102 +
 103 +               port {
 104 +                       hdmi_in_con: endpoint {
 105 +                               remote-endpoint = <&adv7481_hdmi>;
 106 +                       };
 107 +               };
 108 +       };
 109 +
 110 +       hdmi2-in {
 111 +               compatible = "hdmi-connector";
 112 +               label = "HDMI2 IN";
 113 +               type = "a";
 114 +
 115 +               port {
 116 +                       hdmi_in_con2: endpoint {
 117 +                               remote-endpoint = <&adv7481_hdmi2>;
 118 +                       };
 119 +               };
 120 +       };
 121 +
 122 +       reg_1p8v: regulator0 {
 123 +               compatible = "regulator-fixed";
 124 +               regulator-name = "fixed-1.8V";
 125 +               regulator-min-microvolt = <1800000>;
 126 +               regulator-max-microvolt = <1800000>;
 127 +               regulator-boot-on;
 128 +               regulator-always-on;
 129 +       };
 130 +
 131 +       reg_3p3v: regulator1 {
 132 +               compatible = "regulator-fixed";
 133 +               regulator-name = "fixed-3.3V";
 134 +               regulator-min-microvolt = <3300000>;
 135 +               regulator-max-microvolt = <3300000>;
 136 +               regulator-boot-on;
 137 +               regulator-always-on;
 138 +       };
 139 +
 140 +       reg_12v: regulator2 {
 141 +               compatible = "regulator-fixed";
 142 +               regulator-name = "fixed-12V";
 143 +               regulator-min-microvolt = <12000000>;
 144 +               regulator-max-microvolt = <12000000>;
 145 +               regulator-boot-on;
 146 +               regulator-always-on;
 147 +       };
 148 +
 149 +       sound_card: sound {
 150 +               compatible = "audio-graph-card";
 151 +
 152 +               label = "ak4613";
 153 +
 154 +               dais = <&rsnd_port0>;
 155 +       };
 156 +
 157 +       vcc_sdhi0: regulator-vcc-sdhi0 {
 158 +               compatible = "regulator-fixed";
 159 +
 160 +               regulator-name = "SDHI0 Vcc";
 161 +               regulator-min-microvolt = <3300000>;
 162 +               regulator-max-microvolt = <3300000>;
 163 +
 164 +               gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 165 +               enable-active-high;
 166 +       };
 167 +
 168 +       vccq_sdhi0: regulator-vccq-sdhi0 {
 169 +               compatible = "regulator-gpio";
 170 +
 171 +               regulator-name = "SDHI0 VccQ";
 172 +               regulator-min-microvolt = <1800000>;
 173 +               regulator-max-microvolt = <3300000>;
 174 +
 175 +               gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 176 +               gpios-states = <1>;
 177 +               states = <3300000 1
 178 +                         1800000 0>;
 179 +       };
 180 +
 181 +       vcc_sdhi3: regulator-vcc-sdhi3 {
 182 +               compatible = "regulator-fixed";
 183 +
 184 +               regulator-name = "SDHI3 Vcc";
 185 +               regulator-min-microvolt = <3300000>;
 186 +               regulator-max-microvolt = <3300000>;
 187 +
 188 +               gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 189 +               enable-active-high;
 190 +       };
 191 +
 192 +       vccq_sdhi3: regulator-vccq-sdhi3 {
 193 +               compatible = "regulator-gpio";
 194 +
 195 +               regulator-name = "SDHI3 VccQ";
 196 +               regulator-min-microvolt = <1800000>;
 197 +               regulator-max-microvolt = <3300000>;
 198 +
 199 +               gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 200 +               gpios-states = <1>;
 201 +               states = <3300000 1
 202 +                         1800000 0>;
 203 +       };
 204 +
 205 +       hdmi0-out {
 206 +               compatible = "hdmi-connector";
 207 +               label = "HDMI0 OUT";
 208 +               type = "a";
 209 +
 210 +               port {
 211 +                       hdmi0_con: endpoint {
 212 +                       };
 213 +               };
 214 +       };
 215 +
 216 +       hdmi1-out {
 217 +               compatible = "hdmi-connector";
 218 +               label = "HDMI1 OUT";
 219 +               type = "a";
 220 +
 221 +               port {
 222 +                       hdmi1_con: endpoint {
 223 +                       };
 224 +               };
 225 +       };
 226 +
 227 +       x12_clk: x12 {
 228 +               compatible = "fixed-clock";
 229 +               #clock-cells = <0>;
 230 +               clock-frequency = <24576000>;
 231 +       };
 232 +
 233 +       /* External DU dot clocks */
 234 +       x21_clk: x21-clock {
 235 +               compatible = "fixed-clock";
 236 +               #clock-cells = <0>;
 237 +               clock-frequency = <33000000>;
 238 +       };
 239 +
 240 +       x22_clk: x22-clock {
 241 +               compatible = "fixed-clock";
 242 +               #clock-cells = <0>;
 243 +               clock-frequency = <33000000>;
 244 +       };
 245 +
 246 +       x23_clk: x23-clock {
 247 +               compatible = "fixed-clock";
 248 +               #clock-cells = <0>;
 249 +               clock-frequency = <25000000>;
 250 +       };
 251 +};
 252 +
 253 +&a57_0 {
 254 +       cpu-supply = <&dvfs>;
 255 +};
 256 +
 257 +&audio_clk_a {
 258 +       clock-frequency = <22579200>;
 259 +};
 260 +
 261 +&avb {
 262 +       pinctrl-0 = <&avb_pins>;
 263 +       pinctrl-names = "default";
 264 +       phy-handle = <&phy0>;
 265 +       phy-mode = "rgmii-txid";
 266 +       status = "okay";
 267 +
 268 +       phy0: ethernet-phy@0 {
 269 +               rxc-skew-ps = <1500>;
 270 +               reg = <0>;
 271 +               interrupt-parent = <&gpio2>;
 272 +               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 273 +               reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
 274 +       };
 275 +};
 276 +
 277 +&csi40 {
 278 +       status = "okay";
 279 +
 280 +       ports {
 281 +               port@0 {
 282 +                       reg = <0>;
 283 +
 284 +                       csi40_in: endpoint {
 285 +                               clock-lanes = <0>;
 286 +                               data-lanes = <1 2 3 4>;
 287 +                               remote-endpoint = <&adv7481_txa>;
 288 +                       };
 289 +               };
 290 +       };
 291 +};
 292 +
 293 +&csi41 {
 294 +       status = "okay";
 295 +
 296 +       ports {
 297 +               port@0 {
 298 +                       reg = <0>;
 299 +
 300 +                       csi41_in: endpoint {
 301 +                               clock-lanes = <0>;
 302 +                               data-lanes = <1 2 3 4>;
 303 +                               remote-endpoint = <&adv7481_txa2>;
 304 +                       };
 305 +               };
 306 +       };
 307 +};
 308 +
 309 +&du {
 310 +       status = "okay";
 311 +
 312 +};
 313 +
 314 +&ehci0 {
 315 +       dr_mode = "otg";
 316 +       status = "okay";
 317 +};
 318 +
 319 +&ehci1 {
 320 +       status = "okay";
 321 +};
 322 +
 323 +&extalr_clk {
 324 +       clock-frequency = <32768>;
 325 +};
 326 +
 327 +&hscif0 {
 328 +       pinctrl-0 = <&hscif0_pins>;
 329 +       pinctrl-names = "default";
 330 +       uart-has-rtscts;
 331 +
 332 +       status = "okay";
 333 +};
 334 +
 335 +&hscif1 {
 336 +       pinctrl-0 = <&hscif1_pins>;
 337 +       pinctrl-names = "default";
 338 +
 339 +       /* Please use exclusively to the scif1 node */
 340 +       status = "okay";
 341 +};
 342 +
 343 +&hscif2 {
 344 +       pinctrl-0 = <&hscif2_pins>;
 345 +       pinctrl-names = "default";
 346 +
 347 +       status = "okay";
 348 +};
 349 +
 350 +&hsusb {
 351 +       dr_mode = "otg";
 352 +       status = "okay";
 353 +};
 354 +
 355 +&i2c2 {
 356 +       pinctrl-0 = <&i2c2_pins>;
 357 +       pinctrl-names = "default";
 358 +
 359 +       status = "okay";
 360 +
 361 +       clock-frequency = <100000>;
 362 +
 363 +       video-receiver@70 {
 364 +               compatible = "adi,adv7481";
 365 +               reg = <0x70 0x26 0x22 0x34 0x36 0x32
 366 +                      0x31 0x30 0x41 0x79 0x4a 0x48>;
 367 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 368 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 369 +
 370 +               #address-cells = <1>;
 371 +               #size-cells = <0>;
 372 +
 373 +               interrupt-parent = <&gpio0>;
 374 +               interrupt-names = "intrq1", "intrq3";
 375 +               interrupts = <4 IRQ_TYPE_LEVEL_LOW>,
 376 +                            <5 IRQ_TYPE_LEVEL_LOW>;
 377 +
 378 +               port@8 {
 379 +                       reg = <8>;
 380 +
 381 +                       adv7481_hdmi: endpoint {
 382 +                               remote-endpoint = <&hdmi_in_con>;
 383 +                       };
 384 +               };
 385 +
 386 +               port@a {
 387 +                       reg = <10>;
 388 +
 389 +                       adv7481_txa: endpoint {
 390 +                               clock-lanes = <0>;
 391 +                               data-lanes = <1 2 3 4>;
 392 +                               remote-endpoint = <&csi40_in>;
 393 +                       };
 394 +               };
 395 +
 396 +       };
 397 +
 398 +       video-receiver@71 {
 399 +               compatible = "adi,adv7481";
 400 +               reg = <0x71 0x27 0x23 0x35 0x37 0x33
 401 +                      0x28 0x29 0x42 0x78 0x4b 0x49>;
 402 +               reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
 403 +                           "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 404 +
 405 +               #address-cells = <1>;
 406 +               #size-cells = <0>;
 407 +
 408 +               interrupt-parent = <&gpio6>;
 409 +               interrupt-names = "intrq1", "intrq3";
 410 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
 411 +                            <1 IRQ_TYPE_LEVEL_LOW>;
 412 +
 413 +               port@8 {
 414 +                       reg = <8>;
 415 +
 416 +                       adv7481_hdmi2: endpoint {
 417 +                               remote-endpoint = <&hdmi_in_con2>;
 418 +                       };
 419 +               };
 420 +
 421 +               port@a {
 422 +                       reg = <10>;
 423 +
 424 +                       adv7481_txa2: endpoint {
 425 +                               clock-lanes = <0>;
 426 +                               data-lanes = <1 2 3 4>;
 427 +                               remote-endpoint = <&csi41_in>;
 428 +                       };
 429 +               };
 430 +       };
 431 +
 432 +       cs2000: clk_multiplier@4f {
 433 +               #clock-cells = <0>;
 434 +               compatible = "cirrus,cs2000-cp";
 435 +               reg = <0x4f>;
 436 +               clocks = <&audio_clkout>, <&x12_clk>;
 437 +               clock-names = "clk_in", "ref_clk";
 438 +
 439 +               assigned-clocks = <&cs2000>;
 440 +               assigned-clock-rates = <24576000>; /* 1/1 divide */
 441 +       };
 442 +};
 443 +
 444 +&i2c3 {
 445 +       pinctrl-0 = <&i2c3_pins>;
 446 +       pinctrl-names = "default";
 447 +
 448 +       status = "okay";
 449 +
 450 +       clock-frequency = <100000>;
 451 +
 452 +       asm330lhh@6a {
 453 +               compatible = "st,asm330lhh";
 454 +               reg = <0x6a>;
 455 +
 456 +               interrupt-names = "int1", "int2";
 457 +               interrupts = <&gpio6 23 IRQ_TYPE_EDGE_RISING>,
 458 +                            <&gpio2 6 IRQ_TYPE_EDGE_RISING>;
 459 +       };
 460 +};
 461 +
 462 +&i2c4 {
 463 +       status = "okay";
 464 +
 465 +       versaclock5: clock-generator@68 {
 466 +               compatible = "idt,9fgv0841";
 467 +               reg = <0x68>;
 468 +               #clock-cells = <1>;
 469 +               clocks = <&x23_clk>;
 470 +               clock-names = "xin";
 471 +       };
 472 +};
 473 +
 474 +&i2c5 {
 475 +       pinctrl-0 = <&i2c5_pins>;
 476 +       pinctrl-names = "default";
 477 +
 478 +       status = "okay";
 479 +
 480 +       clock-frequency = <100000>;
 481 +
 482 +       ak4613: codec@10 {
 483 +               compatible = "asahi-kasei,ak4613";
 484 +               #sound-dai-cells = <0>;
 485 +               reg = <0x10>;
 486 +               clocks = <&rcar_sound 3>;
 487 +
 488 +               asahi-kasei,in1-single-end;
 489 +               asahi-kasei,in2-single-end;
 490 +               asahi-kasei,out1-single-end;
 491 +               asahi-kasei,out2-single-end;
 492 +               asahi-kasei,out3-single-end;
 493 +               asahi-kasei,out4-single-end;
 494 +               asahi-kasei,out5-single-end;
 495 +               asahi-kasei,out6-single-end;
 496 +
 497 +               port {
 498 +                       ak4613_endpoint: endpoint {
 499 +                               remote-endpoint = <&rsnd_endpoint0>;
 500 +                       };
 501 +               };
 502 +       };
 503 +};
 504 +
 505 +&i2c_dvfs {
 506 +       status = "okay";
 507 +
 508 +       clock-frequency = <400000>;
 509 +
 510 +       pmic: pmic@30 {
 511 +               pinctrl-0 = <&irq0_pins>;
 512 +               pinctrl-names = "default";
 513 +
 514 +               compatible = "rohm,bd9571mwv";
 515 +               reg = <0x30>;
 516 +               interrupt-parent = <&intc_ex>;
 517 +               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 518 +               interrupt-controller;
 519 +               #interrupt-cells = <2>;
 520 +               gpio-controller;
 521 +               #gpio-cells = <2>;
 522 +               rohm,ddr-backup-power = <0xf>;
 523 +               rohm,rstbmode-level;
 524 +
 525 +               regulators {
 526 +                       dvfs: dvfs {
 527 +                               regulator-name = "dvfs";
 528 +                               regulator-min-microvolt = <750000>;
 529 +                               regulator-max-microvolt = <1030000>;
 530 +                               regulator-boot-on;
 531 +                               regulator-always-on;
 532 +                       };
 533 +               };
 534 +       };
 535 +
 536 +       eeprom@50 {
 537 +               compatible = "rohm,br24t01", "atmel,24c01";
 538 +               reg = <0x50>;
 539 +               pagesize = <8>;
 540 +       };
 541 +};
 542 +
 543 +&ohci0 {
 544 +       dr_mode = "otg";
 545 +       status = "okay";
 546 +};
 547 +
 548 +&ohci1 {
 549 +       status = "okay";
 550 +};
 551 +
 552 +&pcie_bus_clk {
 553 +       clock-frequency = <100000000>;
 554 +       status = "okay";
 555 +};
 556 +
 557 +&pciec0 {
 558 +       status = "okay";
 559 +};
 560 +
 561 +&pciec1 {
 562 +       status = "okay";
 563 +};
 564 +
 565 +&canfd {
 566 +       pinctrl-0 = <&canfd0_pins &canfd1_pins>;
 567 +       pinctrl-names = "default";
 568 +
 569 +       status = "okay";
 570 +
 571 +       channel0 {
 572 +               status = "okay";
 573 +       };
 574 +
 575 +       channel1 {
 576 +               status = "okay";
 577 +       };
 578 +};
 579 +
 580 +&pfc {
 581 +       pinctrl-0 = <&scif_clk_pins>;
 582 +       pinctrl-names = "default";
 583 +
 584 +       avb_pins: avb {
 585 +               mux {
 586 +                       groups = "avb_link", "avb_mdio", "avb_mii";
 587 +                       function = "avb";
 588 +               };
 589 +
 590 +               pins_mdio {
 591 +                       groups = "avb_mdio";
 592 +                       drive-strength = <24>;
 593 +               };
 594 +
 595 +               pins_mii_tx {
 596 +                       pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0",
 597 +                              "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";
 598 +                       drive-strength = <12>;
 599 +               };
 600 +       };
 601 +
 602 +       hscif0_pins: hscif0 {
 603 +               groups = "hscif0_data", "hscif0_ctrl";
 604 +               function = "hscif0";
 605 +       };
 606 +
 607 +       hscif1_pins: hscif1 {
 608 +               groups = "hscif1_data_a";
 609 +               function = "hscif1";
 610 +       };
 611 +
 612 +       hscif2_pins: hscif2 {
 613 +               groups = "hscif2_data_c";
 614 +               function = "hscif2";
 615 +       };
 616 +
 617 +       i2c2_pins: i2c2 {
 618 +               groups = "i2c2_a";
 619 +               function = "i2c2";
 620 +       };
 621 +
 622 +       i2c3_pins: i2c3 {
 623 +               groups = "i2c3";
 624 +               function = "i2c3";
 625 +       };
 626 +
 627 +       i2c5_pins: i2c5 {
 628 +               groups = "i2c5";
 629 +               function = "i2c5";
 630 +       };
 631 +
 632 +       irq0_pins: irq0 {
 633 +               groups = "intc_ex_irq0";
 634 +               function = "intc_ex";
 635 +       };
 636 +
 637 +       scif1_pins: scif1 {
 638 +               groups = "scif1_data_b";
 639 +               function = "scif1";
 640 +       };
 641 +
 642 +       scif2_pins: scif2 {
 643 +               groups = "scif2_data_a";
 644 +               function = "scif2";
 645 +       };
 646 +
 647 +       scif5_pins: scif5 {
 648 +               groups = "scif5_data_a";
 649 +               function = "scif5";
 650 +       };
 651 +
 652 +       scif_clk_pins: scif_clk {
 653 +               groups = "scif_clk_a";
 654 +               function = "scif_clk";
 655 +       };
 656 +
 657 +       sdhi0_pins: sd0 {
 658 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 659 +               function = "sdhi0";
 660 +               power-source = <3300>;
 661 +       };
 662 +
 663 +       sdhi0_pins_uhs: sd0_uhs {
 664 +               groups = "sdhi0_data4", "sdhi0_ctrl";
 665 +               function = "sdhi0";
 666 +               power-source = <1800>;
 667 +       };
 668 +
 669 +       sdhi2_pins: sd2 {
 670 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 671 +               function = "sdhi2";
 672 +               power-source = <3300>;
 673 +       };
 674 +
 675 +       sdhi2_pins_uhs: sd2_uhs {
 676 +               groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
 677 +               function = "sdhi2";
 678 +               power-source = <1800>;
 679 +       };
 680 +
 681 +       sdhi3_pins: sd3 {
 682 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 683 +               function = "sdhi3";
 684 +               power-source = <3300>;
 685 +       };
 686 +
 687 +       sdhi3_pins_uhs: sd3_uhs {
 688 +               groups = "sdhi3_data4", "sdhi3_ctrl";
 689 +               function = "sdhi3";
 690 +               power-source = <1800>;
 691 +       };
 692 +
 693 +       sound_pins: sound {
 694 +               groups = "ssi349_ctrl", "ssi3_data", "ssi4_data";
 695 +               function = "ssi";
 696 +       };
 697 +
 698 +       sound_clk_pins: sound_clk {
 699 +               groups = "audio_clk_a_a", "audio_clk_b_a",
 700 +                        "audio_clkout_a", "audio_clkout3_b";
 701 +               function = "audio_clk";
 702 +       };
 703 +
 704 +       usb0_pins: usb0 {
 705 +               groups = "usb0";
 706 +               function = "usb0";
 707 +       };
 708 +
 709 +       usb1_pins: usb1 {
 710 +               groups = "usb1_ovc";
 711 +               function = "usb1";
 712 +       };
 713 +
 714 +       usb30_pins: usb30 {
 715 +               groups = "usb30", "usb30_ovc";
 716 +               function = "usb30";
 717 +       };
 718 +
 719 +       canfd0_pins: canfd0 {
 720 +               groups = "canfd0_data_a";
 721 +               function = "canfd0";
 722 +       };
 723 +
 724 +       canfd1_pins: canfd1 {
 725 +               groups = "canfd1_data";
 726 +               function = "canfd1";
 727 +       };
 728 +};
 729 +
 730 +&rcar_sound {
 731 +       pinctrl-0 = <&sound_pins &sound_clk_pins>;
 732 +       pinctrl-names = "default";
 733 +
 734 +       /* Single DAI */
 735 +       #sound-dai-cells = <0>;
 736 +
 737 +       /* audio_clkout0/1/2/3 */
 738 +       #clock-cells = <1>;
 739 +       clock-frequency = <12288000 11289600>;
 740 +
 741 +       status = "okay";
 742 +
 743 +       /* update <audio_clk_b> to <cs2000> */
 744 +       clocks = <&cpg CPG_MOD 1005>,
 745 +                <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 746 +                <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 747 +                <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 748 +                <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 749 +                <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 750 +                <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 751 +                <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 752 +                <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 753 +                <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 754 +                <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 755 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 756 +                <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
 757 +                <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 758 +                <&audio_clk_a>, <&cs2000>,
 759 +                <&audio_clk_c>,
 760 +                <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
 761 +
 762 +       ports {
 763 +               #address-cells = <1>;
 764 +               #size-cells = <0>;
 765 +               rsnd_port0: port@0 {
 766 +                       reg = <0>;
 767 +                       rsnd_endpoint0: endpoint {
 768 +                               remote-endpoint = <&ak4613_endpoint>;
 769 +
 770 +                               dai-format = "left_j";
 771 +                               bitclock-master = <&rsnd_endpoint0>;
 772 +                               frame-master = <&rsnd_endpoint0>;
 773 +
 774 +                               playback = <&ssi3>; //ssi0 -> ssi3
 775 +                               capture  = <&ssi4>; //ssi1 -> ssi4
 776 +                       };
 777 +               };
 778 +       };
 779 +};
 780 +
 781 +&rwdt {
 782 +       timeout-sec = <60>;
 783 +       status = "okay";
 784 +};
 785 +
 786 +&scif1 {
 787 +       pinctrl-0 = <&scif1_pins>;
 788 +       pinctrl-names = "default";
 789 +
 790 +       uart-has-rtscts;
 791 +       /* Please use exclusively to the hscif1 node */
 792 +       status = "okay";
 793 +};
 794 +
 795 +&scif2 {
 796 +       pinctrl-0 = <&scif2_pins>;
 797 +       pinctrl-names = "default";
 798 +
 799 +       status = "okay";
 800 +};
 801 +
 802 +&scif5 {
 803 +       pinctrl-0 = <&scif5_pins>;
 804 +       pinctrl-names = "default";
 805 +
 806 +       status = "okay";
 807 +};
 808 +
 809 +&scif_clk {
 810 +       clock-frequency = <14745600>;
 811 +};
 812 +
 813 +&sdhi0 {
 814 +       pinctrl-0 = <&sdhi0_pins>;
 815 +       pinctrl-1 = <&sdhi0_pins_uhs>;
 816 +       pinctrl-names = "default", "state_uhs";
 817 +
 818 +       vmmc-supply = <&vcc_sdhi0>;
 819 +       vqmmc-supply = <&vccq_sdhi0>;
 820 +       cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 821 +       wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 822 +       bus-width = <4>;
 823 +       sd-uhs-sdr50;
 824 +       sd-uhs-sdr104;
 825 +       status = "okay";
 826 +};
 827 +
 828 +&sdhi2 {
 829 +       /* used for on-board 8bit eMMC */
 830 +       pinctrl-0 = <&sdhi2_pins>;
 831 +       pinctrl-1 = <&sdhi2_pins_uhs>;
 832 +       pinctrl-names = "default", "state_uhs";
 833 +
 834 +       iommus = <&ipmmu_ds1 34>;
 835 +
 836 +       vmmc-supply = <&reg_3p3v>;
 837 +       vqmmc-supply = <&reg_1p8v>;
 838 +       bus-width = <8>;
 839 +       mmc-hs200-1_8v;
 840 +       mmc-hs400-1_8v;
 841 +       no-sd;
 842 +       no-sdio;
 843 +       non-removable;
 844 +       fixed-emmc-driver-type = <1>;
 845 +       status = "okay";
 846 +};
 847 +
 848 +&sdhi3 {
 849 +       pinctrl-0 = <&sdhi3_pins>;
 850 +       pinctrl-1 = <&sdhi3_pins_uhs>;
 851 +       pinctrl-names = "default", "state_uhs";
 852 +
 853 +       vmmc-supply = <&vcc_sdhi3>;
 854 +       vqmmc-supply = <&vccq_sdhi3>;
 855 +       cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 856 +       wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 857 +       bus-width = <4>;
 858 +       sd-uhs-sdr50;
 859 +       sd-uhs-sdr104;
 860 +       status = "okay";
 861 +};
 862 +
 863 +&ssi4 {
 864 +       shared-pin;
 865 +};
 866 +
 867 +&usb_extal_clk {
 868 +       clock-frequency = <50000000>;
 869 +};
 870 +
 871 +&usb2_phy0 {
 872 +       pinctrl-0 = <&usb0_pins>;
 873 +       pinctrl-names = "default";
 874 +
 875 +       status = "okay";
 876 +};
 877 +
 878 +&usb2_phy1 {
 879 +       pinctrl-0 = <&usb1_pins>;
 880 +       pinctrl-names = "default";
 881 +
 882 +       status = "okay";
 883 +};
 884 +
 885 +&usb3_peri0 {
 886 +       phys = <&usb3_phy0>;
 887 +       phy-names = "usb";
 888 +
 889 +       status = "okay";
 890 +};
 891 +
 892 +&usb3_phy0 {
 893 +       status = "okay";
 894 +};
 895 +
 896 +&usb3s0_clk {
 897 +       clock-frequency = <100000000>;
 898 +};
 899 +
 900 +&vin0 {
 901 +       status = "okay";
 902 +};
 903 +
 904 +&vin1 {
 905 +       status = "okay";
 906 +};
 907 +
 908 +&vin2 {
 909 +       status = "okay";
 910 +};
 911 +
 912 +&vin3 {
 913 +       status = "okay";
 914 +};
 915 +
 916 +&vin4 {
 917 +       status = "okay";
 918 +};
 919 +
 920 +&vin5 {
 921 +       status = "okay";
 922 +};
 923 +
 924 +&vin6 {
 925 +       status = "okay";
 926 +};
 927 +
 928 +&vin7 {
 929 +       status = "okay";
 930 +};
 931 +
 932 +&xhci0 {
 933 +       pinctrl-0 = <&usb30_pins>;
 934 +       pinctrl-names = "default";
 935 +
 936 +       status = "okay";
 937 +};
 938 diff --git a/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 939 new file mode 100644
 940 index 000000000000..0a63d2e7a64b
 941 --- /dev/null
 942 +++ b/arch/arm64/boot/dts/renesas/r8a7795-agl-refhw.dts
 943 @@ -0,0 +1,378 @@
 944 +/*
 945 + * Device Tree Source for the AGL reference hardware board with R-Car H3 ES3.0
 946 + *
 947 + * Copyright (C) 2019 Panasonic Corp.
 948 + * Copyright (C) 2020 Konsulko Group
 949 + *
 950 + * This file is licensed under the terms of the GNU General Public License
 951 + * version 2.  This program is licensed "as is" without any warranty of any
 952 + * kind, whether express or implied.
 953 + */
 954 +
 955 +/*
 956 + * This file is for the most part derived from:
 957 + *
 958 + * - r8a7795-salvator-xs-4x2g.dts
 959 + * - r8a7795-salvator-xs.dts
 960 + * - salvator-xs.dtsi
 961 + *
 962 + * With agl-refhw-common.dtsi replacing (and derived from) salvator-common.dtsi.
 963 + */
 964 +
 965 +/dts-v1/;
 966 +#include "r8a7795.dtsi"
 967 +#include "agl-refhw-common.dtsi"
 968 +
 969 +/ {
 970 +       model = "AGL Reference Hardware based on r8a7795 ES3.0+ with 8GiB (4 x 2 GiB)";
 971 +       compatible = "agl,refhw-h3", "renesas,r8a7795";
 972 +
 973 +       memory@48000000 {
 974 +               device_type = "memory";
 975 +               /* first 128MB is reserved for secure area. */
 976 +               reg = <0x0 0x48000000 0x0 0x78000000>;
 977 +       };
 978 +
 979 +       memory@500000000 {
 980 +               device_type = "memory";
 981 +               reg = <0x5 0x00000000 0x0 0x80000000>;
 982 +       };
 983 +
 984 +       memory@600000000 {
 985 +               device_type = "memory";
 986 +               reg = <0x6 0x00000000 0x0 0x80000000>;
 987 +       };
 988 +
 989 +       memory@700000000 {
 990 +               device_type = "memory";
 991 +               reg = <0x7 0x00000000 0x0 0x80000000>;
 992 +       };
 993 +
 994 +       reserved-memory {
 995 +               #address-cells = <2>;
 996 +               #size-cells = <2>;
 997 +               ranges;
 998 +
 999 +               /* device specific region for Lossy Decompression */
1000 +               lossy_decompress: linux,lossy_decompress@54000000 {
1001 +                       no-map;
1002 +                       reg = <0x00000000 0x54000000 0x0 0x03000000>;
1003 +               };
1004 +
1005 +               /* For Audio DSP */
1006 +               adsp_reserved: linux,adsp@57000000 {
1007 +                       compatible = "shared-dma-pool";
1008 +                       reusable;
1009 +                       reg = <0x00000000 0x57000000 0x0 0x01000000>;
1010 +               };
1011 +
1012 +               /* global autoconfigured region for contiguous allocations */
1013 +               linux,cma@58000000 {
1014 +                       compatible = "shared-dma-pool";
1015 +                       reusable;
1016 +                       reg = <0x00000000 0x58000000 0x0 0x18000000>;
1017 +                       linux,cma-default;
1018 +               };
1019 +
1020 +               /* device specific region for contiguous allocations */
1021 +               mmp_reserved: linux,multimedia@70000000 {
1022 +                       compatible = "shared-dma-pool";
1023 +                       reusable;
1024 +                       reg = <0x00000000 0x70000000 0x0 0x10000000>;
1025 +               };
1026 +       };
1027 +
1028 +       mmngr {
1029 +               compatible = "renesas,mmngr";
1030 +               memory-region = <&mmp_reserved>, <&lossy_decompress>;
1031 +       };
1032 +
1033 +       mmngrbuf {
1034 +               compatible = "renesas,mmngrbuf";
1035 +       };
1036 +
1037 +       vspm_if {
1038 +               compatible = "renesas,vspm_if";
1039 +       };
1040 +
1041 +       vga {
1042 +               port {
1043 +                       vga_in: endpoint {
1044 +                               /delete-property/remote-endpoint;
1045 +                       };
1046 +               };
1047 +       };
1048 +
1049 +       vga-encoder {
1050 +               ports {
1051 +                       port@0 {
1052 +                               adv7123_in: endpoint {
1053 +                                       /delete-property/remote-endpoint;
1054 +                               };
1055 +                       };
1056 +
1057 +                       port@1 {
1058 +                               adv7123_out: endpoint {
1059 +                                       /delete-property/remote-endpoint;
1060 +                               };
1061 +                       };
1062 +               };
1063 +       };
1064 +
1065 +};
1066 +
1067 +&adsp {
1068 +       status = "okay";
1069 +       memory-region = <&adsp_reserved>;
1070 +};
1071 +
1072 +&du {
1073 +       clocks = <&cpg CPG_MOD 724>,
1074 +                <&cpg CPG_MOD 723>,
1075 +                <&cpg CPG_MOD 722>,
1076 +                <&cpg CPG_MOD 721>,
1077 +                <&versaclock6 1>,
1078 +                <&x21_clk>,
1079 +                <&x22_clk>,
1080 +                <&versaclock6 2>;
1081 +       clock-names = "du.0", "du.1", "du.2", "du.3",
1082 +                     "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
1083 +};
1084 +
1085 +&ehci2 {
1086 +       status = "okay";
1087 +};
1088 +
1089 +&ehci3 {
1090 +       dr_mode = "otg";
1091 +       status = "okay";
1092 +};
1093 +
1094 +&hsusb3 {
1095 +       dr_mode = "otg";
1096 +       status = "okay";
1097 +};
1098 +
1099 +&sound_card {
1100 +       dais = <&rsnd_port0     /* ak4613 */
1101 +               &rsnd_port1     /* HDMI0  */
1102 +               &rsnd_port2>;   /* HDMI1  */
1103 +};
1104 +
1105 +&hdmi0 {
1106 +       status = "okay";
1107 +
1108 +       ports {
1109 +               port@1 {
1110 +                       reg = <1>;
1111 +                       rcar_dw_hdmi0_out: endpoint {
1112 +                               remote-endpoint = <&hdmi0_con>;
1113 +                       };
1114 +               };
1115 +               port@2 {
1116 +                       reg = <2>;
1117 +                       dw_hdmi0_snd_in: endpoint {
1118 +                               remote-endpoint = <&rsnd_endpoint1>;
1119 +                       };
1120 +               };
1121 +       };
1122 +};
1123 +
1124 +&hdmi0_con {
1125 +       remote-endpoint = <&rcar_dw_hdmi0_out>;
1126 +};
1127 +
1128 +&hdmi1 {
1129 +       status = "okay";
1130 +
1131 +       ports {
1132 +               port@1 {
1133 +                       reg = <1>;
1134 +                       rcar_dw_hdmi1_out: endpoint {
1135 +                               remote-endpoint = <&hdmi1_con>;
1136 +                       };
1137 +               };
1138 +               port@2 {
1139 +                       reg = <2>;
1140 +                       dw_hdmi1_snd_in: endpoint {
1141 +                               remote-endpoint = <&rsnd_endpoint2>;
1142 +                       };
1143 +               };
1144 +       };
1145 +};
1146 +
1147 +&hdmi1_con {
1148 +       remote-endpoint = <&rcar_dw_hdmi1_out>;
1149 +};
1150 +
1151 +&ohci2 {
1152 +       status = "okay";
1153 +};
1154 +
1155 +&ohci3 {
1156 +       dr_mode = "otg";
1157 +       status = "okay";
1158 +};
1159 +
1160 +&rcar_sound {
1161 +       ports {
1162 +               /* rsnd_port0 is on salvator-common */
1163 +               rsnd_port1: port@1 {
1164 +                       reg = <1>;
1165 +                       rsnd_endpoint1: endpoint {
1166 +                               remote-endpoint = <&dw_hdmi0_snd_in>;
1167 +
1168 +                               dai-format = "i2s";
1169 +                               bitclock-master = <&rsnd_endpoint1>;
1170 +                               frame-master = <&rsnd_endpoint1>;
1171 +
1172 +                               playback = <&ssi2>;
1173 +                       };
1174 +               };
1175 +               rsnd_port2: port@2 {
1176 +                       reg = <2>;
1177 +                       rsnd_endpoint2: endpoint {
1178 +                               remote-endpoint = <&dw_hdmi1_snd_in>;
1179 +
1180 +                               dai-format = "i2s";
1181 +                               bitclock-master = <&rsnd_endpoint2>;
1182 +                               frame-master = <&rsnd_endpoint2>;
1183 +
1184 +                               playback = <&ssi3>;
1185 +                       };
1186 +               };
1187 +       };
1188 +};
1189 +
1190 +&pfc {
1191 +       usb2_pins: usb2 {
1192 +               groups = "usb2", "usb2_ovc";
1193 +               function = "usb2";
1194 +       };
1195 +
1196 +       /*
1197 +        * - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
1198 +        *   (when SW31 is the default setting on Salvator-XS).
1199 +        * - If SW31 is the default setting, you cannot use USB2.0 ch3 on
1200 +        *   r8a7795 with Salvator-XS.
1201 +        *   Hence the SW31 setting must be changed like 2) below.
1202 +        *   1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
1203 +        *      - Connect GP6_3[01] to ADV7842.
1204 +        *   2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
1205 +        *      - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
1206 +        *      - Connect GP6_{04,21} to ADV7842.
1207 +        */
1208 +       usb2_ch3_pins: usb2_ch3 {
1209 +               groups = "usb2_ch3";
1210 +               function = "usb2_ch3";
1211 +       };
1212 +};
1213 +
1214 +&usb2_phy2 {
1215 +       pinctrl-0 = <&usb2_pins>;
1216 +       pinctrl-names = "default";
1217 +
1218 +       status = "okay";
1219 +};
1220 +
1221 +&usb2_phy3 {
1222 +       pinctrl-0 = <&usb2_ch3_pins>;
1223 +       pinctrl-names = "default";
1224 +
1225 +       status = "okay";
1226 +};
1227 +
1228 +&vspbc {
1229 +       status = "okay";
1230 +};
1231 +
1232 +&vspbd {
1233 +       status = "okay";
1234 +};
1235 +
1236 +&vspi0 {
1237 +       status = "okay";
1238 +};
1239 +
1240 +&vspi1 {
1241 +       status = "okay";
1242 +};
1243 +
1244 +/* End r8a7795-salvator-xs.dts content */
1245 +
1246 +
1247 +/* Start r8a7795-salvator-xs-4x2g.dts content */
1248 +
1249 +&pciec0 {
1250 +       /* Map all possible DDR as inbound ranges */
1251 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1252 +};
1253 +
1254 +&pciec1 {
1255 +       /* Map all possible DDR as inbound ranges */
1256 +       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
1257 +};
1258 +
1259 +/* End r8a7795-salvator-xs-4x2g.dts content */
1260 +
1261 +
1262 +/* Start salvator-xs.dts content */
1263 +
1264 +&extal_clk {
1265 +       clock-frequency = <16640000>;
1266 +};
1267 +
1268 +&i2c4 {
1269 +       clock-frequency = <400000>;
1270 +
1271 +       versaclock6: clock-generator@6a {
1272 +               compatible = "idt,5p49v6901";
1273 +               reg = <0x6a>;
1274 +               #clock-cells = <1>;
1275 +               clocks = <&x23_clk>;
1276 +               clock-names = "xin";
1277 +       };
1278 +};
1279 +
1280 +/* End salvator-xs.dts content */
1281 +
1282 +
1283 +/* Start reference hardware specific tweaks */
1284 +
1285 +&du {
1286 +       ports {
1287 +               port@0 {
1288 +                       endpoint {
1289 +                               /delete-property/remote-endpoint;
1290 +                       };
1291 +               };
1292 +
1293 +               port@3 {
1294 +                       endpoint {
1295 +                               /delete-property/remote-endpoint;
1296 +                       };
1297 +               };
1298 +       };
1299 +};
1300 +
1301 +&lvds0 {
1302 +       status = "disabled";
1303 +};
1304 +
1305 +&pwm1 {
1306 +       status = "disabled";
1307 +};
1308 +
1309 +&scif_clk {
1310 +       clock-frequency = <0>;
1311 +};
1312 +
1313 +&sdhi0 {
1314 +       /delete-property/ wp-gpios;
1315 +       non-removable;
1316 +};
1317 +
1318 +&sdhi3 {
1319 +       /delete-property/ wp-gpios;
1320 +       non-removable;
1321 +};
1322 diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c
1323 index 87092ce5ba73..357c334113aa 100644
1324 --- a/drivers/media/i2c/adv748x/adv748x-core.c
1325 +++ b/drivers/media/i2c/adv748x/adv748x-core.c
1326 @@ -97,6 +97,21 @@ static const struct adv748x_register_map adv748x_default_addresses[] = {
1327         [ADV748X_PAGE_TXA] = { "txa", 0x4a },
1328  };
1329
1330 +static const struct adv748x_register_map adv748x_default_addresses2[] = {
1331 +       [ADV748X_PAGE_IO] = { "main", 0x71 },
1332 +       [ADV748X_PAGE_DPLL] = { "dpll", 0x27 },
1333 +       [ADV748X_PAGE_CP] = { "cp", 0x23 },
1334 +       [ADV748X_PAGE_HDMI] = { "hdmi", 0x35 },
1335 +       [ADV748X_PAGE_EDID] = { "edid", 0x37 },
1336 +       [ADV748X_PAGE_REPEATER] = { "repeater", 0x33 },
1337 +       [ADV748X_PAGE_INFOFRAME] = { "infoframe", 0x28 },
1338 +       [ADV748X_PAGE_CBUS] = { "cbus", 0x29 },
1339 +       [ADV748X_PAGE_CEC] = { "cec", 0x42 },
1340 +       [ADV748X_PAGE_SDP] = { "sdp", 0x78 },
1341 +       [ADV748X_PAGE_TXB] = { "txb", 0x49 },
1342 +       [ADV748X_PAGE_TXA] = { "txa", 0x4b },
1343 +};
1344 +
1345  static int adv748x_read_check(struct adv748x_state *state,
1346                               int client_page, u8 reg)
1347  {
1348 @@ -183,10 +198,17 @@ static int adv748x_initialise_clients(struct adv748x_state *state)
1349         int ret;
1350
1351         for (i = ADV748X_PAGE_DPLL; i < ADV748X_PAGE_MAX; ++i) {
1352 -               state->i2c_clients[i] = i2c_new_ancillary_device(
1353 +               if ((state->client->addr << 1) == 0xe0) {
1354 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1355                                 state->client,
1356                                 adv748x_default_addresses[i].name,
1357                                 adv748x_default_addresses[i].default_addr);
1358 +               } else {
1359 +                       state->i2c_clients[i] = i2c_new_ancillary_device(
1360 +                               state->client,
1361 +                               adv748x_default_addresses2[i].name,
1362 +                               adv748x_default_addresses2[i].default_addr);
1363 +               }
1364
1365                 if (IS_ERR(state->i2c_clients[i])) {
1366                         adv_err(state, "failed to create i2c client %u\n", i);