1 From 80d5c1269bd16fedce41611e45f25d156425b0c9 Mon Sep 17 00:00:00 2001
2 From: Yuichi Kusakabe <yuichi.kusakabe@jp.fujitsu.com>
3 Date: Fri, 19 May 2017 16:16:18 +0900
4 Subject: [PATCH 4/4] Add porter board Hibernation code
6 Signed-off-by: Yuichi Kusakabe <yuichi.kusakabe@jp.fujitsu.com>
8 arch/arm/cpu/armv7/Makefile | 4 +
9 arch/arm/cpu/armv7/arch_timer.c | 58 ++++++
10 arch/arm/cpu/armv7/cache_v7.c | 14 +-
11 arch/arm/cpu/armv7/rmobile/Makefile | 4 +
12 arch/arm/cpu/armv7/rmobile/arm_arch_timer.c | 61 ++++++
13 arch/arm/cpu/armv7/rmobile/crc32_word4.c | 299 ++++++++++++++++++++++++++++
14 arch/arm/cpu/armv7/rmobile/crc32_word4.h | 23 +++
15 arch/arm/cpu/armv7/rmobile/sh_timer.c | 209 +++++++++++++++++++
16 arch/arm/include/asm/arch-rmobile/rmobile.h | 2 +
17 arch/arm/include/asm/armv7.h | 16 +-
18 arch/arm/include/asm/system.h | 136 ++++++++++++-
19 arch/arm/lib/Makefile | 2 +
20 arch/arm/lib/board.c | 2 +-
21 arch/arm/lib/cache-cp15.c | 123 +++++++++++-
22 arch/arm/lib/call_with_stack.S | 20 ++
23 board/renesas/porter/porter.c | 10 +
24 include/configs/porter.h | 19 +-
25 17 files changed, 977 insertions(+), 25 deletions(-)
26 create mode 100644 arch/arm/cpu/armv7/arch_timer.c
27 create mode 100644 arch/arm/cpu/armv7/rmobile/arm_arch_timer.c
28 create mode 100644 arch/arm/cpu/armv7/rmobile/crc32_word4.c
29 create mode 100644 arch/arm/cpu/armv7/rmobile/crc32_word4.h
30 create mode 100644 arch/arm/cpu/armv7/rmobile/sh_timer.c
31 create mode 100644 arch/arm/lib/call_with_stack.S
33 diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
34 index 4fdbee4..f68ce5c 100644
35 --- a/arch/arm/cpu/armv7/Makefile
36 +++ b/arch/arm/cpu/armv7/Makefile
37 @@ -32,6 +32,10 @@ COBJS += cache_v7.o
41 +ifneq ($(CONFIG_SYS_ARCH_TIMER),)
42 +COBJS += arch_timer.o
45 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
46 SOBJS += lowlevel_init.o
48 diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c
50 index 0000000..747b6e9
52 +++ b/arch/arm/cpu/armv7/arch_timer.c
55 + * (C) Copyright 2012-2014
56 + * Texas Instruments Incorporated, <www.ti.com>
58 + * SPDX-License-Identifier: GPL-2.0+
65 +DECLARE_GLOBAL_DATA_PTR;
72 + gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
77 +unsigned long long get_ticks(void)
81 + asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (nowl), "=r" (nowu));
86 + return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
90 +ulong get_timer(ulong base)
92 + return lldiv(get_ticks(), gd->timer_rate_hz) - base;
95 +void __udelay(unsigned long usec)
97 + unsigned long long endtime;
99 + endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
102 + endtime += get_ticks();
104 + while (get_ticks() < endtime)
108 +ulong get_tbclk(void)
110 + return gd->timer_rate_hz;
112 diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
113 index 5f6d039..5a0bdb8 100644
114 --- a/arch/arm/cpu/armv7/cache_v7.c
115 +++ b/arch/arm/cpu/armv7/cache_v7.c
116 @@ -82,7 +82,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
119 /* DSB to make sure the operation is complete */
124 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
125 @@ -109,7 +109,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
128 /* DSB to make sure the operation is complete */
133 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
134 @@ -230,7 +230,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
137 /* DSB to make sure the operation is complete */
143 @@ -243,9 +243,9 @@ static void v7_inval_tlb(void)
144 /* Invalidate entire instruction TLB */
145 asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
146 /* Full system DSB - make sure that the invalidation is complete */
149 /* Full system ISB - make sure the instruction stream sees it */
154 void invalidate_dcache_all(void)
155 @@ -356,10 +356,10 @@ void invalidate_icache_all(void)
156 asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
158 /* Full system DSB - make sure that the invalidation is complete */
162 /* ISB - make sure the instruction stream sees it */
167 void invalidate_icache_all(void)
168 diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
169 index b8c04c6..0a3623a 100644
170 --- a/arch/arm/cpu/armv7/rmobile/Makefile
171 +++ b/arch/arm/cpu/armv7/rmobile/Makefile
172 @@ -46,6 +46,10 @@ COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o
173 COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
174 COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
175 COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o
176 +COBJS-$(CONFIG_SYS_ARCH_TIMER) += arm_arch_timer.o
177 +ifeq ($(CONFIG_CMD_SWSUSP),y)
178 +COBJS-y += crc32_word4.o
182 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
183 diff --git a/arch/arm/cpu/armv7/rmobile/arm_arch_timer.c b/arch/arm/cpu/armv7/rmobile/arm_arch_timer.c
185 index 0000000..a499e71
187 +++ b/arch/arm/cpu/armv7/rmobile/arm_arch_timer.c
190 + * Copyright (C) 2014 Cogent Embedded Inc.
192 + * Licensed under the GPL-2 or later.
198 +#define MODEMR 0xe6160060
199 +#define MD(x) (1 << (x))
200 +#define CNTCR 0xe6080000
201 +#define CNTFID0 0xe6080020
203 +void arm_arch_timer_init(void)
205 + u32 mode = readl(MODEMR);
208 + switch (mode & (MD(14) | MD(13))) {
215 + case MD(13) | MD(14):
223 + freq *= (1000000 / 2);
225 +#ifdef CONFIG_VE_ENABLED
226 + /* CNTVOFF has to be initialized either from non-secure Hypervisor
227 + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
228 + * then it should be handled by the secure code
232 + " mrc p15, 0, r1, c1, c1, 0\n"
233 + " orr r0, r1, #1\n"
234 + " mcr p15, 0, r0, c1, c1, 0\n"
237 + " mcrr p15, 4, r0, r0, c14\n"
239 + " mcr p15, 0, r1, c1, c1, 0\n"
245 + /* Start Generic ARM timer */
246 + writel(freq, CNTFID0);
247 + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
250 diff --git a/arch/arm/cpu/armv7/rmobile/crc32_word4.c b/arch/arm/cpu/armv7/rmobile/crc32_word4.c
252 index 0000000..b813899
254 +++ b/arch/arm/cpu/armv7/rmobile/crc32_word4.c
256 +/*************************************************************************
257 + * crc32_word4.c: rapid CRC32
258 + * Coptright (C) FUJITSUTEN Limited, 2015 All Rights Reserved.
260 + * This program is free software; you can redistribute it and/or modify
261 + * it under the terms of the GNU General Public License version 2
262 + * as published by the Free Software Foundation.
264 + * This program is distributed in the hope that it will be useful,
265 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
266 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
267 + * GNU General Public License for more details.
269 + * You should have received a copy of the GNU General Public License
270 + * along with this program; if not, write to the Free Software Foundation,
271 + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
272 + *************************************************************************/
277 +#include <asm/types.h>
278 +typedef unsigned int u_int32_t;
283 +#include "crc32_word4.h"
285 +#define CRC_INIT_VALUE (-1)
286 +#define CRC_FIX(_crc32) (~(_crc32))
288 +#define __HWDTPLS_OUT()
289 +#define MEASURE(msg)
291 +/**** calc_crc32.c *****/
294 + * CRC32は、ISO 3309 で規程され
296 + * RFC 2083 :PNG(Poratble Network Graphics
297 + * で公になっています。本プログラムは、RFC2083 で掲示された
298 + * CRC32を独自に最適化したプログラムです。
300 +const static u_int32_t CRC_Table[256] = {
301 + 0x00000000 , 0x77073096 , 0xee0e612c , 0x990951ba , 0x076dc419 , 0x706af48f , 0xe963a535 , 0x9e6495a3 ,
302 + 0x0edb8832 , 0x79dcb8a4 , 0xe0d5e91e , 0x97d2d988 , 0x09b64c2b , 0x7eb17cbd , 0xe7b82d07 , 0x90bf1d91 ,
303 + 0x1db71064 , 0x6ab020f2 , 0xf3b97148 , 0x84be41de , 0x1adad47d , 0x6ddde4eb , 0xf4d4b551 , 0x83d385c7 ,
304 + 0x136c9856 , 0x646ba8c0 , 0xfd62f97a , 0x8a65c9ec , 0x14015c4f , 0x63066cd9 , 0xfa0f3d63 , 0x8d080df5 ,
305 + 0x3b6e20c8 , 0x4c69105e , 0xd56041e4 , 0xa2677172 , 0x3c03e4d1 , 0x4b04d447 , 0xd20d85fd , 0xa50ab56b ,
306 + 0x35b5a8fa , 0x42b2986c , 0xdbbbc9d6 , 0xacbcf940 , 0x32d86ce3 , 0x45df5c75 , 0xdcd60dcf , 0xabd13d59 ,
307 + 0x26d930ac , 0x51de003a , 0xc8d75180 , 0xbfd06116 , 0x21b4f4b5 , 0x56b3c423 , 0xcfba9599 , 0xb8bda50f ,
308 + 0x2802b89e , 0x5f058808 , 0xc60cd9b2 , 0xb10be924 , 0x2f6f7c87 , 0x58684c11 , 0xc1611dab , 0xb6662d3d ,
309 + 0x76dc4190 , 0x01db7106 , 0x98d220bc , 0xefd5102a , 0x71b18589 , 0x06b6b51f , 0x9fbfe4a5 , 0xe8b8d433 ,
310 + 0x7807c9a2 , 0x0f00f934 , 0x9609a88e , 0xe10e9818 , 0x7f6a0dbb , 0x086d3d2d , 0x91646c97 , 0xe6635c01 ,
311 + 0x6b6b51f4 , 0x1c6c6162 , 0x856530d8 , 0xf262004e , 0x6c0695ed , 0x1b01a57b , 0x8208f4c1 , 0xf50fc457 ,
312 + 0x65b0d9c6 , 0x12b7e950 , 0x8bbeb8ea , 0xfcb9887c , 0x62dd1ddf , 0x15da2d49 , 0x8cd37cf3 , 0xfbd44c65 ,
313 + 0x4db26158 , 0x3ab551ce , 0xa3bc0074 , 0xd4bb30e2 , 0x4adfa541 , 0x3dd895d7 , 0xa4d1c46d , 0xd3d6f4fb ,
314 + 0x4369e96a , 0x346ed9fc , 0xad678846 , 0xda60b8d0 , 0x44042d73 , 0x33031de5 , 0xaa0a4c5f , 0xdd0d7cc9 ,
315 + 0x5005713c , 0x270241aa , 0xbe0b1010 , 0xc90c2086 , 0x5768b525 , 0x206f85b3 , 0xb966d409 , 0xce61e49f ,
316 + 0x5edef90e , 0x29d9c998 , 0xb0d09822 , 0xc7d7a8b4 , 0x59b33d17 , 0x2eb40d81 , 0xb7bd5c3b , 0xc0ba6cad ,
317 + 0xedb88320 , 0x9abfb3b6 , 0x03b6e20c , 0x74b1d29a , 0xead54739 , 0x9dd277af , 0x04db2615 , 0x73dc1683 ,
318 + 0xe3630b12 , 0x94643b84 , 0x0d6d6a3e , 0x7a6a5aa8 , 0xe40ecf0b , 0x9309ff9d , 0x0a00ae27 , 0x7d079eb1 ,
319 + 0xf00f9344 , 0x8708a3d2 , 0x1e01f268 , 0x6906c2fe , 0xf762575d , 0x806567cb , 0x196c3671 , 0x6e6b06e7 ,
320 + 0xfed41b76 , 0x89d32be0 , 0x10da7a5a , 0x67dd4acc , 0xf9b9df6f , 0x8ebeeff9 , 0x17b7be43 , 0x60b08ed5 ,
321 + 0xd6d6a3e8 , 0xa1d1937e , 0x38d8c2c4 , 0x4fdff252 , 0xd1bb67f1 , 0xa6bc5767 , 0x3fb506dd , 0x48b2364b ,
322 + 0xd80d2bda , 0xaf0a1b4c , 0x36034af6 , 0x41047a60 , 0xdf60efc3 , 0xa867df55 , 0x316e8eef , 0x4669be79 ,
323 + 0xcb61b38c , 0xbc66831a , 0x256fd2a0 , 0x5268e236 , 0xcc0c7795 , 0xbb0b4703 , 0x220216b9 , 0x5505262f ,
324 + 0xc5ba3bbe , 0xb2bd0b28 , 0x2bb45a92 , 0x5cb36a04 , 0xc2d7ffa7 , 0xb5d0cf31 , 0x2cd99e8b , 0x5bdeae1d ,
325 + 0x9b64c2b0 , 0xec63f226 , 0x756aa39c , 0x026d930a , 0x9c0906a9 , 0xeb0e363f , 0x72076785 , 0x05005713 ,
326 + 0x95bf4a82 , 0xe2b87a14 , 0x7bb12bae , 0x0cb61b38 , 0x92d28e9b , 0xe5d5be0d , 0x7cdcefb7 , 0x0bdbdf21 ,
327 + 0x86d3d2d4 , 0xf1d4e242 , 0x68ddb3f8 , 0x1fda836e , 0x81be16cd , 0xf6b9265b , 0x6fb077e1 , 0x18b74777 ,
328 + 0x88085ae6 , 0xff0f6a70 , 0x66063bca , 0x11010b5c , 0x8f659eff , 0xf862ae69 , 0x616bffd3 , 0x166ccf45 ,
329 + 0xa00ae278 , 0xd70dd2ee , 0x4e048354 , 0x3903b3c2 , 0xa7672661 , 0xd06016f7 , 0x4969474d , 0x3e6e77db ,
330 + 0xaed16a4a , 0xd9d65adc , 0x40df0b66 , 0x37d83bf0 , 0xa9bcae53 , 0xdebb9ec5 , 0x47b2cf7f , 0x30b5ffe9 ,
331 + 0xbdbdf21c , 0xcabac28a , 0x53b39330 , 0x24b4a3a6 , 0xbad03605 , 0xcdd70693 , 0x54de5729 , 0x23d967bf ,
332 + 0xb3667a2e , 0xc4614ab8 , 0x5d681b02 , 0x2a6f2b94 , 0xb40bbe37 , 0xc30c8ea1 , 0x5a05df1b , 0x2d02ef8d ,
336 + * CRC Table creater.
338 +void make_crc_table(void) {
341 + for (n = 0; n < 256; n++)
344 + for (k = 0; k < 8; k++)
347 + c = 0xedb88320L ^ (c >> 1);
355 +#define NEXT_PTR (4)
358 +u_int32_t _update_crc(u_int32_t crc, unsigned char *buf, size_t len)
362 + for (n = 0; n < len; n++)
363 + c = CRC_Table[(c ^ buf[n]) & 0xff] ^ (c >> 8);
366 +/*********************************************************************
367 + * update_crc4x4()()
368 + * calc_crc32() をベースに、4 ワード毎に個別に CRC32 を計算する方法
371 + * +0x00 AAAAAAAA BBBBBBBB CCCCCCCC DDDDDDDD
372 + * +0x04 EEEEEEEE FFFFFFFF 00000000 11111111
374 + * CRC32 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
376 + *********************************************************************/
379 +void update_crc4x4(u_int32_t crc[4], unsigned char *buf)
381 + u_int32_t c1, c2, c3, c4;
382 + u_int32_t *p = (void *)buf;
384 + c1 = crc[0] ^ p[0];
385 + c2 = crc[1] ^ p[1];
386 + c3 = crc[2] ^ p[2];
387 + c4 = crc[3] ^ p[3];
389 + c1 = CRC_Table[c1 & 0xff] ^ (c1 >> 8);
390 + c2 = CRC_Table[c2 & 0xff] ^ (c2 >> 8);
391 + c3 = CRC_Table[c3 & 0xff] ^ (c3 >> 8);
392 + c4 = CRC_Table[c4 & 0xff] ^ (c4 >> 8);
394 + c1 = CRC_Table[c1 & 0xff] ^ (c1 >> 8);
395 + c2 = CRC_Table[c2 & 0xff] ^ (c2 >> 8);
396 + c3 = CRC_Table[c3 & 0xff] ^ (c3 >> 8);
397 + c4 = CRC_Table[c4 & 0xff] ^ (c4 >> 8);
399 + c1 = CRC_Table[c1 & 0xff] ^ (c1 >> 8);
400 + c2 = CRC_Table[c2 & 0xff] ^ (c2 >> 8);
401 + c3 = CRC_Table[c3 & 0xff] ^ (c3 >> 8);
402 + c4 = CRC_Table[c4 & 0xff] ^ (c4 >> 8);
404 + c1 = CRC_Table[c1 & 0xff] ^ (c1 >> 8);
405 + c2 = CRC_Table[c2 & 0xff] ^ (c2 >> 8);
406 + c3 = CRC_Table[c3 & 0xff] ^ (c3 >> 8);
407 + c4 = CRC_Table[c4 & 0xff] ^ (c4 >> 8);
416 +void calc_crc32x4(unsigned char *buf, size_t len, CRC32_WORD4_t *result)
418 + unsigned int crc_tmp[4] = {CRC_INIT_VALUE, CRC_INIT_VALUE, CRC_INIT_VALUE, CRC_INIT_VALUE};
423 +#ifdef HWDPLS_ENABLE
424 + unsigned long plstout = 60;
425 + unsigned long plsstart = 0;
426 + if ((unsigned long)CONFIG_SYS_HZ > 100000)
427 + plstout *= (unsigned long)CONFIG_SYS_HZ / 1000;
429 + plstout = DIV_ROUND_UP(plstout * (unsigned long)CONFIG_SYS_HZ, 1000);
433 + * 4バイト境界に合わない開始アドレスの場合
434 + * 境界までのCRCを crc_tmp[0] に求める。
436 + if ((unsigned long)buf & 3) {
437 + crc_tmp[0] = _update_crc(crc_tmp[0], buf, (unsigned long)buf & 3);
438 + buf = (unsigned char *)((unsigned long)buf & ~3);
439 + xlen -= (unsigned long)buf & 3;
442 + n4 = xlen/(NEXT_PTR*4);
444 + * 4バイト境界に合わない開始アドレスの場合
445 + * 境界までのCRCを crc_tmp[0] に求める。
447 +#ifdef HWDPLS_ENABLE
449 + plsstart = get_timer(0);
451 + for (i = 0; i < n4 ; i++) {
452 + update_crc4x4(crc_tmp, buf);
453 + buf += NEXT_PTR * 4;
454 +#ifdef HWDPLS_ENABLE
458 + if (__builtin_expect((int)((i & 0x1f) == 0), 0)) {
459 + if ((get_timer(plsstart)) > plstout) {
461 + MEASURE("crc plsout")
462 + plsstart += plstout;
465 +#endif /*HWPLS_ENABLE*/
468 + res = xlen % (NEXT_PTR * 4);
470 + crc_tmp[3] = _update_crc(crc_tmp[3], buf, res);
472 + result->crc_w[0] = CRC_FIX(crc_tmp[0]);
473 + result->crc_w[1] = CRC_FIX(crc_tmp[1]);
474 + result->crc_w[2] = CRC_FIX(crc_tmp[2]);
475 + result->crc_w[3] = CRC_FIX(crc_tmp[3]);
477 + MEASURE("calc_crc32x4 finish")
480 +#if defined(OWNTEST)
481 +#define BUFSIZE (2 * 1024 * 1024)
482 +#include <sys/time.h>
487 + unsigned char *buf, *buf2;
488 + struct timeval start, end;
489 + unsigned long long diff;
492 + CRC32_WORD4_t result = { .crc_w = {0, 0, 0, 0 } };
493 + CRC32_WORD4_t result2 = { .crc_w = {0, 0, 0, 0 } };
495 + buf = malloc(BUFSIZE);
500 + printf("Generate %dMB random data..\n", BUFSIZE / 1024 / 1024);
502 + for (i = 0; i < BUFSIZE / 4; i++)
503 + ((int *)buf)[i] = rand();
506 + buf2 = memalign(NEXT_PTR, BUFSIZE);
511 + memcpy(buf2, buf, BUFSIZE);
514 + gettimeofday(&start, NULL);
515 + calc_crc32x4(buf, BUFSIZE, &result);
516 + gettimeofday(&end, NULL);
518 + diff = (end.tv_sec - start.tv_sec) * 1000000;
519 + diff += end.tv_usec - start.tv_usec;
521 + printf("time=%lluus\n", diff);
522 + printf(" result.word[0] = %x\n", result.crc_w[0]);
523 + printf(" result.word[1] = %x\n", result.crc_w[1]);
524 + printf(" result.word[2] = %x\n", result.crc_w[2]);
525 + printf(" result.word[3] = %x\n", result.crc_w[3]);
528 +#if 0 /* Destory test */
529 + buf[rand() % BUFSIZE] ^= 1 << (rand()%7);
531 + for (i = 0; i < BUFSIZE ; i++) {
532 + if (buf[i] != buf2[i])
533 + printf("buf[%d] %02x : %02x\n", i, buf[i], buf2[i]);
536 + gettimeofday(&start, NULL);
537 + calc_crc32x4(buf, BUFSIZE, &result2);
538 + gettimeofday(&end, NULL);
540 + diff = (end.tv_sec - start.tv_sec) * 1000000;
541 + diff += end.tv_usec - start.tv_usec;
543 + printf("time=%lluus\n", diff);
544 + printf(" result.word[0] = %x:%s\n", result2.crc_w[0] ,
545 + result.crc_w[0] == result2.crc_w[0] ? "OK" : "NG");
546 + printf(" result.word[1] = %x:%s\n", result2.crc_w[1] ,
547 + result.crc_w[1] == result2.crc_w[1] ? "OK" : "NG");
548 + printf(" result.word[2] = %x:%s\n", result2.crc_w[2] ,
549 + result.crc_w[2] == result2.crc_w[2] ? "OK" : "NG");
550 + printf(" result.word[3] = %x:%s\n", result2.crc_w[3] ,
551 + result.crc_w[3] == result2.crc_w[3] ? "OK" : "NG");
555 diff --git a/arch/arm/cpu/armv7/rmobile/crc32_word4.h b/arch/arm/cpu/armv7/rmobile/crc32_word4.h
557 index 0000000..2b64218
559 +++ b/arch/arm/cpu/armv7/rmobile/crc32_word4.h
561 +/*************************************************************************
562 + * Coptright (C) FUJITSUTEN Limited, 2012 All Rights Reserved.
564 + *************************************************************************/
565 +#ifndef __CRC32_WORD4_H__
566 +#define __CRC32_WORD4_H__
569 + unsigned int crc_w[4];
572 +void calc_crc32x4(unsigned char *buf, size_t len, CRC32_WORD4_t *result);
576 + CRC32_WORD4_t chksum;
577 + unsigned int dummy[3];
578 +} CRC32_WORD4_TICKET_t;
580 +#define IS_CRC_WORD4_OK(_res1, _res2) (!memcmp((_res1), (_res2), sizeof(CRC32_WORD4_t)))
581 +#define IS_CRC_WORD4_ZERO(_w4) (((_w4)->crc_w[0] == 0) && ((_w4)->crc_w[1] == 0) && ((_w4)->crc_w[2] == 0) && ((_w4)->crc_w[3] == 0))
582 +#define IS_CRC_WORD4_ALL_F(_w4) (((_w4)->crc_w[0] == 0xffffffff) && ((_w4)->crc_w[1] == 0xffffffff) && ((_w4)->crc_w[2] == 0xffffffff) && ((_w4)->crc_w[3] == 0xffffffff))
584 diff --git a/arch/arm/cpu/armv7/rmobile/sh_timer.c b/arch/arm/cpu/armv7/rmobile/sh_timer.c
586 index 0000000..1c64950
588 +++ b/arch/arm/cpu/armv7/rmobile/sh_timer.c
591 + * Copyright (C) 2013-2014 Renesas Electronics Corporation
593 + * (C) Copyright 2009
594 + * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
596 + * (C) Copyright 2007-2012
597 + * Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
599 + * (C) Copyright 2003
600 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
602 + * See file CREDITS for list of people who contributed to this
605 + * This program is free software; you can redistribute it and/or
606 + * modify it under the terms of the GNU General Public License as
607 + * published by the Free Software Foundation; either version 2 of
608 + * the License, or (at your option) any later version.
610 + * This program is distributed in the hope that it will be useful,
611 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
612 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
613 + * GNU General Public License for more details.
615 + * You should have received a copy of the GNU General Public License
616 + * along with this program; if not, write to the Free Software
617 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
618 + * MA 02111-1307 USA
623 +#include <asm/processor.h>
627 +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
628 + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
630 +DECLARE_GLOBAL_DATA_PTR;
634 +static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
637 +static unsigned long last_tcnt;
638 +static unsigned long long overflow_ticks;
640 +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
641 + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
643 +unsigned long get_tbclk(void)
645 + if (gd->flags & GD_FLG_RELOC)
646 + return get_tmu0_clk_rate() >> ((bit + 1) * 2);
650 + bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
651 + return get_tmu0_clk_rate() >> ((bit + 1) * 2);
657 +unsigned long get_tbclk(void)
659 + return get_tmu0_clk_rate() >> ((bit + 1) * 2);
664 +static inline unsigned long long tick_to_time(unsigned long long tick)
666 + tick *= CONFIG_SYS_HZ;
667 + do_div(tick, get_tbclk());
672 +static inline unsigned long long usec_to_tick(unsigned long long usec)
674 + usec *= get_tbclk();
675 + do_div(usec, 1000000);
680 +static void tmu_timer_start(unsigned int timer)
684 + writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr);
687 +static void tmu_timer_stop(unsigned int timer)
691 + writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr);
694 +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
695 + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
697 +int sh_timer_init(void)
699 + bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
700 + writew((readw(&tmu->tcr0) & ~0x7) | bit, &tmu->tcr0);
703 + tmu_timer_start(0);
706 + overflow_ticks = 0;
711 +int timer_init(void)
714 + tmu_timer_start(0);
721 +int timer_init(void)
723 + bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) >> 1) - 1;
724 + writew((readw(&tmu->tcr0) & ~0x7) | bit, &tmu->tcr0);
727 + tmu_timer_start(0);
730 + overflow_ticks = 0;
737 +#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
738 + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
740 +unsigned long long get_ticks(void)
742 + unsigned long tcnt = 0 - readl(&tmu->tcnt0);
744 + if (gd->flags & GD_FLG_RELOC) {
745 + if (last_tcnt > tcnt) /* overflow */
749 + return (overflow_ticks << 32) | tcnt;
757 +unsigned long long get_ticks(void)
759 + unsigned long tcnt = 0 - readl(&tmu->tcnt0);
761 + if (last_tcnt > tcnt) /* overflow */
765 + return (overflow_ticks << 32) | tcnt;
770 +void __udelay(unsigned long usec)
772 + unsigned long long tmp;
775 + tmo = usec_to_tick(usec);
776 + tmp = get_ticks() + tmo; /* get current timestamp */
778 + while (get_ticks() < tmp) /* loop till event */
782 +unsigned long get_timer(unsigned long base)
785 + return tick_to_time(get_ticks()) - base;
788 +void set_timer(unsigned long t)
790 + writel((0 - t), &tmu->tcnt0);
793 +void reset_timer(void)
797 + tmu_timer_start(0);
799 diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
800 index 33a302e..12276e0 100644
801 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h
802 +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
803 @@ -26,6 +26,8 @@ u32 rmobile_get_cpu_type(void);
804 u32 rmobile_get_cpu_rev_integer(void);
805 u32 rmobile_get_cpu_rev_fraction(void);
807 +void arm_arch_timer_init(void);
809 #endif /* __ASSEMBLY__ */
811 #endif /* __KERNEL__ */
812 diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
813 index ad9a875..aad5bf7 100644
814 --- a/arch/arm/include/asm/armv7.h
815 +++ b/arch/arm/include/asm/armv7.h
817 * However, we use the CP15 based instructtions because we use
818 * -march=armv5 in U-Boot
820 -#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
821 -#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
822 -#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
823 +#define CP15ISB() asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
824 +#define CP15DSB() asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
825 +#define CP15DMB() asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
827 +#ifdef __ARM_ARCH_7A__
828 +#define ISB() asm volatile ("isb" : : : "memory")
829 +#define DSB() asm volatile ("dsb" : : : "memory")
830 +#define DMB() asm volatile ("dmb" : : : "memory")
832 +#define ISB() CP15ISB
833 +#define DSB() CP15DSB
834 +#define DMB() CP15DMB
837 void v7_outer_cache_enable(void);
838 void v7_outer_cache_disable(void);
839 diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
840 index cd0de6b..3906646 100644
841 --- a/arch/arm/include/asm/system.h
842 +++ b/arch/arm/include/asm/system.h
844 #define CR_AFE (1 << 29) /* Access flag enable */
845 #define CR_TE (1 << 30) /* Thumb exception enable */
847 +#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
848 +#define PGTABLE_SIZE (4096 * 5)
849 +#elif !defined(PGTABLE_SIZE)
850 +#define PGTABLE_SIZE (4096 * 4)
854 * This is used to ensure the compiler did actually allocate the register we
855 * asked it for some inline assembly sequences. Apparently we can't trust
858 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
860 +static inline unsigned long get_cpsr(void)
862 + unsigned long cpsr;
864 + asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
868 +static inline int is_hyp(void)
870 +#ifdef CONFIG_ARMV7_LPAE
871 + /* HYP mode requires LPAE ... */
872 + return ((get_cpsr() & 0x1f) == 0x1a);
874 + /* ... so without LPAE support we can optimize all hyp code away */
879 static inline unsigned int get_cr(void)
882 - asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
885 + asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
889 + asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
895 static inline void set_cr(unsigned int val)
897 - asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
898 - : : "r" (val) : "cc");
900 + asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
904 + asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
910 @@ -105,19 +144,108 @@ static inline void set_actlr(unsigned int val)
914 +#ifdef CONFIG_ARMV7_LPAE
915 +/* Long-Descriptor Translation Table Level 1/2 Bits */
916 +#define TTB_SECT_XN_MASK (1ULL << 54)
917 +#define TTB_SECT_NG_MASK (1 << 11)
918 +#define TTB_SECT_AF (1 << 10)
919 +#define TTB_SECT_SH_MASK (3 << 8)
920 +#define TTB_SECT_NS_MASK (1 << 5)
921 +#define TTB_SECT_AP (1 << 6)
922 +/* Note: TTB AP bits are set elsewhere */
923 +#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
924 +#define TTB_SECT (1 << 0)
925 +#define TTB_PAGETABLE (3 << 0)
928 +#define TTBCR_EAE (1 << 31)
929 +#define TTBCR_T0SZ(x) ((x) << 0)
930 +#define TTBCR_T1SZ(x) ((x) << 16)
931 +#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
932 +#define TTBCR_IRGN0_NC (0 << 8)
933 +#define TTBCR_IRGN0_WBWA (1 << 8)
934 +#define TTBCR_IRGN0_WT (2 << 8)
935 +#define TTBCR_IRGN0_WBNWA (3 << 8)
936 +#define TTBCR_IRGN0_MASK (3 << 8)
937 +#define TTBCR_ORGN0_NC (0 << 10)
938 +#define TTBCR_ORGN0_WBWA (1 << 10)
939 +#define TTBCR_ORGN0_WT (2 << 10)
940 +#define TTBCR_ORGN0_WBNWA (3 << 10)
941 +#define TTBCR_ORGN0_MASK (3 << 10)
942 +#define TTBCR_SHARED_NON (0 << 12)
943 +#define TTBCR_SHARED_OUTER (2 << 12)
944 +#define TTBCR_SHARED_INNER (3 << 12)
945 +#define TTBCR_EPD0 (0 << 7)
950 +#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
951 + (0xcc << (2 * 8)) | (0xff << (3 * 8)))
953 +/* options available for data cache on each page */
954 +enum dcache_option {
955 + DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
956 + DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
957 + DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
958 + DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
960 +#elif defined(CONFIG_ARMV7)
961 +/* Short-Descriptor Translation Table Level 1 Bits */
962 +#define TTB_SECT_NS_MASK (1 << 19)
963 +#define TTB_SECT_NG_MASK (1 << 17)
964 +#define TTB_SECT_S_MASK (1 << 16)
965 +/* Note: TTB AP bits are set elsewhere */
966 +#define TTB_SECT_AP (3 << 10)
967 +#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
968 +#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
969 +#define TTB_SECT_XN_MASK (1 << 4)
970 +#define TTB_SECT_C_MASK (1 << 3)
971 +#define TTB_SECT_B_MASK (1 << 2)
972 +#define TTB_SECT (2 << 0)
974 +/* options available for data cache on each page */
975 +enum dcache_option {
976 + DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
977 + DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
978 + DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
979 + DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
982 +#define TTB_SECT_AP (3 << 10)
983 /* options available for data cache on each page */
986 DCACHE_WRITETHROUGH = 0x1a,
987 DCACHE_WRITEBACK = 0x1e,
988 + DCACHE_WRITEALLOC = 0x16,
992 /* Size of an MMU section */
994 - MMU_SECTION_SHIFT = 20,
995 +#ifdef CONFIG_ARMV7_LPAE
996 + MMU_SECTION_SHIFT = 21, /* 2MB */
998 + MMU_SECTION_SHIFT = 20, /* 1MB */
1000 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
1003 +#ifdef CONFIG_ARMV7
1005 +#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
1006 +#define TTBR0_RGN_NC (0 << 3)
1007 +#define TTBR0_RGN_WBWA (1 << 3)
1008 +#define TTBR0_RGN_WT (2 << 3)
1009 +#define TTBR0_RGN_WB (3 << 3)
1010 +/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
1011 +#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
1012 +#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
1013 +#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
1014 +#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
1018 * Change the cache settings for a region.
1020 diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
1021 index 57111af..d8634be 100644
1022 --- a/arch/arm/lib/Makefile
1023 +++ b/arch/arm/lib/Makefile
1024 @@ -54,6 +54,8 @@ COBJS-y += reset.o
1026 COBJS-y += cache-cp15.o
1028 +COBJS-y += call_with_stack.o
1030 SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
1031 $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
1032 OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
1033 diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
1034 index 9f861cc..3c2bf55 100644
1035 --- a/arch/arm/lib/board.c
1036 +++ b/arch/arm/lib/board.c
1037 @@ -355,7 +355,7 @@ void board_init_f(ulong bootflag)
1039 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
1040 /* reserve TLB table */
1041 - gd->tlb_size = 4096 * 4;
1042 + gd->tlb_size = PGTABLE_SIZE;
1043 addr -= gd->tlb_size;
1045 /* round down to next 64 kB limit */
1046 diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
1047 index 75cf7b1..aefa2ae 100644
1048 --- a/arch/arm/lib/cache-cp15.c
1049 +++ b/arch/arm/lib/cache-cp15.c
1050 @@ -44,13 +44,50 @@ static void cp_delay (void)
1051 asm volatile("" : : : "memory");
1054 +#ifdef CONFIG_ARMV7_LPAE
1055 +struct special_addr {
1061 +/* This hack is for 2GB board with second GB attached
1062 + * to LPAE-only address at 0x200000000ULL */
1063 +#define SDRAM2_ADDR 0x200000000ULL
1064 +#define SDRAM2_SIZE 0x40000000 /* 1G */
1065 +static struct special_addr offsets[] = {
1066 + { 0x80000000 >> MMU_SECTION_SHIFT, SDRAM2_SIZE >> MMU_SECTION_SHIFT, SDRAM2_ADDR, },
1070 void set_section_dcache(int section, enum dcache_option option)
1072 +#ifdef CONFIG_ARMV7_LPAE
1074 + u64 *page_table = (u64 *)gd->tlb_addr;
1075 + /* Need to set the access flag to not fault */
1076 + u64 value = TTB_SECT_AP | TTB_SECT_AF;
1078 u32 *page_table = (u32 *)gd->tlb_addr;
1080 + u32 value = TTB_SECT_AP;
1083 + /* Add the page offset */
1084 +#ifdef CONFIG_ARMV7_LPAE
1085 + for (i = 0; i < ARRAY_SIZE(offsets); i++)
1086 + if (section >= offsets[i].page &&
1087 + section < offsets[i].page + offsets[i].size)
1088 + value |= offsets[i].addr + ((section - offsets[i].page) << MMU_SECTION_SHIFT);
1090 + value |= ((u32)section << MMU_SECTION_SHIFT);
1092 + value |= ((u32)section << MMU_SECTION_SHIFT);
1095 - value = (section << MMU_SECTION_SHIFT) | (3 << 10);
1096 + /* Add caching bits */
1100 page_table[section] = value;
1103 @@ -66,11 +103,11 @@ void mmu_set_region_dcache_behaviour(u32 start, int size,
1104 enum dcache_option option)
1106 u32 *page_table = (u32 *)gd->tlb_addr;
1108 + unsigned long upto, end;
1110 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
1111 start = start >> MMU_SECTION_SHIFT;
1112 - debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
1113 + debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
1115 for (upto = start; upto < end; upto++)
1116 set_section_dcache(upto, option);
1117 @@ -83,11 +120,14 @@ static inline void dram_bank_mmu_setup(int bank)
1120 debug("%s: bank: %d\n", __func__, bank);
1121 - for (i = bd->bi_dram[bank].start >> 20;
1122 - i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
1123 + for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
1124 + i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
1125 + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
1127 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
1128 set_section_dcache(i, DCACHE_WRITETHROUGH);
1129 +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
1130 + set_section_dcache(i, DCACHE_WRITEALLOC);
1132 set_section_dcache(i, DCACHE_WRITEBACK);
1134 @@ -102,19 +142,88 @@ static inline void mmu_setup(void)
1136 arm_init_before_mmu();
1137 /* Set up an identity-mapping for all 4GB, rw for everyone */
1138 - for (i = 0; i < 4096; i++)
1139 + for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
1140 set_section_dcache(i, DCACHE_OFF);
1142 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1143 dram_bank_mmu_setup(i);
1145 + /* Enabling d-cache for remapped region of memory
1148 + for (i = (0x80000000 >> MMU_SECTION_SHIFT);
1149 + i < 0xc0000000 >> MMU_SECTION_SHIFT; i++)
1150 +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
1151 + set_section_dcache(i, DCACHE_WRITETHROUGH);
1152 +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
1153 + set_section_dcache(i, DCACHE_WRITEALLOC);
1155 + set_section_dcache(i, DCACHE_WRITEBACK);
1158 +#ifdef CONFIG_ARMV7_LPAE
1159 + /* Set up 4 PTE entries pointing to our 4 1GB page tables */
1160 + for (i = 0; i < 4; i++) {
1161 + u64 *page_table = (u64 *)(gd->tlb_addr + (4096 * 4));
1162 + u64 tpt = gd->tlb_addr + (4096 * i);
1163 + page_table[i] = tpt | TTB_PAGETABLE;
1167 +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
1168 + reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
1169 +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
1170 + reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
1172 + reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
1176 + /* Set HCTR to enable LPAE */
1177 + asm volatile("mcr p15, 4, %0, c2, c0, 2"
1178 + : : "r" (reg) : "memory");
1180 + asm volatile("mcrr p15, 4, %0, %1, c2"
1182 + : "r"(gd->tlb_addr + (4096 * 4)), "r"(0)
1185 + asm volatile("mcr p15, 4, %0, c10, c2, 0"
1186 + : : "r" (MEMORY_ATTRIBUTES) : "memory");
1188 + /* Set TTBCR to enable LPAE */
1189 + asm volatile("mcr p15, 0, %0, c2, c0, 2"
1190 + : : "r" (reg) : "memory");
1191 + /* Set 64-bit TTBR0 */
1192 + asm volatile("mcrr p15, 0, %0, %1, c2"
1194 + : "r"(gd->tlb_addr + (4096 * 4)), "r"(0)
1197 + asm volatile("mcr p15, 0, %0, c10, c2, 0"
1198 + : : "r" (MEMORY_ATTRIBUTES) : "memory");
1200 +#elif defined(CONFIG_ARMV7)
1202 + reg = gd->tlb_addr & TTBR0_BASE_ADDR_MASK;
1203 +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
1204 + reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
1205 +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
1206 + reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
1208 + reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
1210 + asm volatile("mcr p15, 0, %0, c2, c0, 0"
1211 + : : "r" (reg) : "memory");
1213 /* Copy the page table address to cp15 */
1214 asm volatile("mcr p15, 0, %0, c2, c0, 0"
1215 : : "r" (gd->tlb_addr) : "memory");
1217 /* Set the access control to all-supervisor */
1218 asm volatile("mcr p15, 0, %0, c3, c0, 0"
1221 /* and enable the mmu */
1222 reg = get_cr(); /* get control reg. */
1224 diff --git a/arch/arm/lib/call_with_stack.S b/arch/arm/lib/call_with_stack.S
1225 new file mode 100644
1226 index 0000000..651d869
1228 +++ b/arch/arm/lib/call_with_stack.S
1230 +.globl call_with_stack
1231 +.syntax unified /* use unified assembler syntax */
1233 +.thumb /* assemble in Thumb-2 (.thumb" can also be used) */
1236 + str sp, [r2, #-4]!
1237 + str lr, [r2, #-4]!
1250 diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
1251 index 71836e2..6c4fd1a 100644
1252 --- a/board/renesas/porter/porter.c
1253 +++ b/board/renesas/porter/porter.c
1254 @@ -42,6 +42,10 @@ void s_init(void)
1255 struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
1258 +#ifdef CONFIG_SYS_ARCH_TIMER
1259 + arm_arch_timer_init();
1263 writel(0xA5A5A500, &rwdt->rwtcsra);
1264 writel(0xA5A5A500, &swdt->swtcsra);
1265 @@ -71,10 +75,12 @@ int board_early_init_f(void)
1269 +#ifdef CONFIG_TMU_TIMER
1271 val = readl(MSTPSR1);
1272 val &= ~TMU0_MSTP125;
1273 writel(val, SMSTPCR1);
1276 val = readl(MSTPSR7);
1277 val &= ~SCIF0_MSTP721;
1278 @@ -114,7 +120,9 @@ int board_init(void)
1279 /* Init PFC controller */
1280 r8a7791_pinmux_init();
1282 +#ifdef CONFIG_TMU_TIMER
1287 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
1288 @@ -288,10 +296,12 @@ void arch_preboot_os()
1292 +#ifdef CONFIG_TMU_TIMER
1294 val = readb(TMU_BASE + TSTR0);
1296 writeb(val, TMU_BASE + TSTR0);
1299 /* stop all module clock*/
1300 for (i = MSTP00; i < MSTP_NR; i++) {
1301 diff --git a/include/configs/porter.h b/include/configs/porter.h
1302 index 7ab0643..5567c7c 100644
1303 --- a/include/configs/porter.h
1304 +++ b/include/configs/porter.h
1306 #define CONFIG_CMD_EXT4_WRITE
1307 #define CONFIG_CMD_SF
1308 #define CONFIG_CMD_SPI
1309 +#define CONFIG_CMD_SWSUSP
1310 +#define CONFIG_CMD_SWSUSPMEM
1313 #define CONFIG_CMDLINE_TAG
1314 #define CONFIG_SETUP_MEMORY_TAGS
1316 #define CONFIG_BOARD_EARLY_INIT_F
1317 #define CONFIG_USE_ARCH_MEMSET
1318 #define CONFIG_USE_ARCH_MEMCPY
1319 -#define CONFIG_TMU_TIMER
1322 #if defined(CONFIG_EXTRAM_BOOT)
1326 #define PORTER_SDRAM_BASE 0x40000000
1327 -#define PORTER_SDRAM_SIZE 0x40000000
1328 -#define PORTER_UBOOT_SDRAM_SIZE 0x20000000
1329 +#define PORTER_SDRAM_SIZE 0x48000000
1330 +#define PORTER_UBOOT_SDRAM_SIZE 0x40000000
1332 #define CONFIG_SYS_LONGHELP
1333 #define CONFIG_SYS_PROMPT "=> "
1334 @@ -203,4 +205,15 @@
1335 #define CONFIG_USB_HOST_ETHER /* Enable USB Ethernet adapters */
1336 #define CONFIG_USB_ETHER_ASIX /* Asix, or whatever driver(s) you want */
1338 +#define CONFIG_ARMV7_LPAE /* 64-bit MMU descriptors */
1339 +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC /* Make memory operations faster */
1341 +#define CONFIG_SYS_ARCH_TIMER /* Init arch timer */
1342 +#define CONFIG_VE_ENABLED /* Virtualization Extensions are enabled*/
1343 +#define CONFIG_SYS_HZ_CLOCK CONFIG_SYS_CLK_FREQ
1345 +#define CONFIG_SH_DMA
1346 +#define CONFIG_SH_SYS_DMAL_BASE 0xE6700000
1347 +#define CONFIG_SH_SYS_DMAL_NCH 15
1349 #endif /* __PORTER_H */