meta-agl-bsp/meta-renesas/recipes-bsp/u-boot/u-boot/hibernation/0001-Add-hibernation-image-area.patch

   1 From 0b5f63c7224cb5c9a00397f0e0ef4a16aa58e516 Mon Sep 17 00:00:00 2001
   2 From: Yuichi Kusakabe <yuichi.kusakabe@jp.fujitsu.com>
   3 Date: Fri, 9 Jun 2017 20:43:06 +0900
   4 Subject: [PATCH 1/3] Add hibernation image area
   5
   6 0x40000000 <-> 0x77FFFFFF : kernel
   7 0x78000000 <-> 0x7FFFFFFF : hibernation image area
   8 and Enable sdhi DMA support
   9
  10 Signed-off-by: Yuichi Kusakabe <yuichi.kusakabe@jp.fujitsu.com>
  11 ---
  12  arch/arm/include/asm/arch-rmobile/r8a7791.h |  3 +++
  13  arch/arm/include/asm/armv7.h                |  3 +++
  14  include/configs/porter.h                    | 24 ++++++++++++------------
  15  3 files changed, 18 insertions(+), 12 deletions(-)
  16
  17 diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
  18 index c964f13..9e08da4 100644
  19 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
  20 +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
  21 @@ -147,6 +147,8 @@
  22
  23  #define DBSC3_0_DBADJ2         0xE67900C8
  24  #define DBSC3_1_DBADJ2         0xE67A00C8
  25 +#define DBSC3_0_DBCALTR                0xE67900F8
  26 +#define DBSC3_1_DBCALTR                0xE67A00F8
  27
  28  #define CCI_400_MAXOT_1                0xF0091110
  29  #define CCI_400_MAXOT_2                0xF0092110
  30 @@ -154,6 +156,7 @@
  31  #define CCI_400_QOSCNTL_2      0xF009210C
  32
  33  #define        MXI_BASE                0xFE960000
  34 +#define        MXI_VIN_QOS             0xFE96020C
  35  #define        MXI_QOS_BASE            0xFE960300
  36
  37  #define SYS_AXI_SYX64TO128_BASE        0xFF800300
  38 diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
  39 index aad5bf7..0d4d612 100644
  40 --- a/arch/arm/include/asm/armv7.h
  41 +++ b/arch/arm/include/asm/armv7.h
  42 @@ -31,6 +31,9 @@
  43  #define MIDR_CORTEX_A9_R1P3    0x411FC093
  44  #define MIDR_CORTEX_A9_R2P10   0x412FC09A
  45
  46 +/* valid bits in CBAR register / PERIPHBASE value */
  47 +#define CBAR_MASK              0xFFFF8000
  48 +
  49  /* Cortex-A15 revisions */
  50  #define MIDR_CORTEX_A15_R0P0   0x410FC0F0
  51
  52 diff --git a/include/configs/porter.h b/include/configs/porter.h
  53 index 5567c7c..f652bab 100644
  54 --- a/include/configs/porter.h
  55 +++ b/include/configs/porter.h
  56 @@ -91,14 +91,14 @@
  57
  58  /* MEMORY */
  59  #define PORTER_SDRAM_BASE      0x40000000
  60 -#define PORTER_SDRAM_SIZE      0x48000000
  61 +#define PORTER_SDRAM_SIZE      0x80000000
  62  #define PORTER_UBOOT_SDRAM_SIZE        0x40000000
  63
  64  #define CONFIG_SYS_LONGHELP
  65  #define CONFIG_SYS_PROMPT              "=> "
  66 -#define CONFIG_SYS_CBSIZE              512
  67 -#define CONFIG_SYS_PBSIZE              512
  68 -#define CONFIG_SYS_MAXARGS             32
  69 +#define CONFIG_SYS_CBSIZE              256
  70 +#define CONFIG_SYS_PBSIZE              256
  71 +#define CONFIG_SYS_MAXARGS             16
  72  #define CONFIG_SYS_BARGSIZE            512
  73  #define CONFIG_SYS_BAUDRATE_TABLE      { 38400, 115200 }
  74
  75 @@ -205,15 +205,15 @@
  76  #define CONFIG_USB_HOST_ETHER  /* Enable USB Ethernet adapters */
  77  #define CONFIG_USB_ETHER_ASIX  /* Asix, or whatever driver(s) you want */
  78
  79 -#define CONFIG_ARMV7_LPAE               /* 64-bit MMU descriptors */
  80 -#define CONFIG_SYS_ARM_CACHE_WRITEALLOC /* Make memory operations faster */
  81 -
  82 -#define CONFIG_SYS_ARCH_TIMER           /* Init arch timer */
  83 -#define CONFIG_VE_ENABLED               /* Virtualization Extensions are enabled*/
  84 -#define CONFIG_SYS_HZ_CLOCK             CONFIG_SYS_CLK_FREQ
  85 +#define CONFIG_ARMV7_LPAE              /* 64-bit MMU descriptors */
  86 +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC        /* Make memory operations faster */
  87 +#define CONFIG_SYS_ARCH_TIMER  /* Init arch timer */
  88 +#define CONFIG_SYS_HZ_CLOCK    CONFIG_SYS_CLK_FREQ
  89
  90 +#if 1
  91  #define CONFIG_SH_DMA
  92 -#define CONFIG_SH_SYS_DMAL_BASE         0xE6700000
  93 -#define CONFIG_SH_SYS_DMAL_NCH          15
  94 +#define CONFIG_SH_SYS_DMAL_BASE                0xE6700000
  95 +#define CONFIG_SH_SYS_DMAL_NCH         15
  96 +#endif
  97
  98  #endif /* __PORTER_H */
  99 --
 100 1.8.3.1
 101