meta-agl-bsp/meta-rcar-gen3/recipes-kernel/linux/files/r8a77960-ulcb-xen.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
   4  *
   5  * Copyright (C) 2016-2018 Renesas Electronics Corp.
   6  * Copyright (C) 2016 Cogent Embedded, Inc.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a77960.dtsi"
  11 #include "ulcb.dtsi"
  12
  13 / {
  14         model = "Renesas M3ULCB board based on r8a7796";
  15         compatible = "renesas,m3ulcb", "renesas,r8a7796";
  16
  17
  18         chosen {
  19                 /delete-property/ bootargs;
  20                 xen,xen-bootargs = "dom0_mem=752M console=dtuart dtuart=serial0 dom0_max_vcpus=4";
  21                 xen,dom0-bootargs = "console=hvc0 clk_ignore_unused root=/dev/mmcblk1p2 rw rootwait ignore_loglevel cma=32M earlyprintk";
  22
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 modules {
  26                         module@0 {
  27                                 compatible = "xen,linux-zimage",
  28                                 "xen,multiboot-module";
  29                                 reg = <0x0 0x7a000000 0x0 0x02000000>;
  30                         };
  31                 };
  32         };
  33
  34         cpus {
  35                 idle-states {
  36                         /delete-node/ cpu-sleep-1;
  37                 };
  38         };
  39
  40         memory@48000000 {
  41                 device_type = "memory";
  42                 /* first 128MB is reserved for secure area. */
  43                 reg = <0x0 0x48000000 0x0 0x38000000>, <0x6 0x00000000 0x0 0x40000000>;
  44         };
  45
  46         vspm_if {
  47                 compatible = "renesas,vspm_if";
  48         };
  49
  50         versaclock5_out3: versaclk-3 {
  51                 compatible = "fixed-clock";
  52                 #clock-cells = <0>;
  53                 /* Initial value of versaclock out3 */
  54                 clock-frequency = <33000000>;
  55         };
  56 };
  57
  58 &a53_0 {
  59         /delete-property/ cpu-idle-states;
  60 };
  61
  62 &a53_1 {
  63         /delete-property/ cpu-idle-states;
  64 };
  65
  66 &a53_2 {
  67         /delete-property/ cpu-idle-states;
  68 };
  69
  70 &a53_3 {
  71         /delete-property/ cpu-idle-states;
  72 };
  73
  74 &du {
  75         clocks = <&cpg CPG_MOD 724>,
  76                  <&cpg CPG_MOD 723>,
  77                  <&cpg CPG_MOD 722>,
  78                  <&versaclock5 1>,
  79                  <&versaclock5_out3>,
  80                  <&versaclock5 2>;
  81         clock-names = "du.0", "du.1", "du.2",
  82                       "dclkin.0", "dclkin.1", "dclkin.2";
  83 };
  84
  85 &vspb {
  86         status = "okay";
  87 };
  88
  89 &vspi0 {
  90         status = "okay";
  91 };