meta-agl-bsp/meta-rcar-gen3/recipes-bsp/arm-trusted-firmware/files/0001-fix-build-for-gcc6-for-h3-init_dram.patch

   1 diff --git a/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h b/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h
   2 index b6edfb5..5d3bcc6 100644
   3 --- a/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h
   4 +++ b/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h
   5 @@ -49,7 +49,7 @@
   6  #define PI_TCCDMW 0x20
   7  #define PI_TDQSCK_MAX 0x6
   8  //////////////////////////////////////////////////////////////////////////////
   9 -#define PI_MR1  0xd4   //MRW DeviceFeature1(Post=1.5tck nWR=30 RDpre=static WRPre=2tCK BL=16//OK
  10 +#define PI_MR1  0xd4U  //MRW DeviceFeature1(Post=1.5tck nWR=30 RDpre=static WRPre=2tCK BL=16//OK
  11  #define PI_MR2  0x2e   //MRW DeviceFeature2(0,0SetA,101=WL14,110=RL32(nRTP14))//NG
  12  #define PI_MR3  0x31
  13  #define PI_MR11 0x36
  14 diff --git a/plat/renesas/rcar/ddr/H3/WS11/init_dram_tbl_h3_ws11.h b/plat/renesas/rcar/ddr/H3/WS11/init_dram_tbl_h3_ws11.h
  15 index 370f87f..971cb0b 100644
  16 --- a/plat/renesas/rcar/ddr/H3/WS11/init_dram_tbl_h3_ws11.h
  17 +++ b/plat/renesas/rcar/ddr/H3/WS11/init_dram_tbl_h3_ws11.h
  18 @@ -28,7 +28,7 @@
  19  #define PI_TCCDMW 0x20
  20  #define PI_TDQSCK_MAX 0x6
  21  //////////////////////////////////////////////////////////////////////////////
  22 -#define PI_MR1  0xd4
  23 +#define PI_MR1  0xd4U
  24  #define PI_MR2  0x2e
  25  #define PI_MR3  0x31
  26  #define PI_MR11 0x36