meta-agl-bsp/meta-rcar-gateway/recipes-kernel/linux/linux-renesas/0001-Porting-to-support-device-driver-Canfd-from-Control-.patch

   1 From a7e7a8317d5b150a97a08270ddfb711a88168add Mon Sep 17 00:00:00 2001
   2 From: Phat Pham <phat.pham.zg@renesas.com>
   3 Date: Wed, 2 Aug 2023 17:12:09 +0700
   4 Subject: [PATCH] Porting to support device driver Canfd from Control Domain to
   5  Application Domain
   6
   7 - Update pinctrl support for 15 canfd channels in file pfc-r8a779f0.c.
   8 - Update device tree to support GPIO Group 4-7 on CA55 in file r8a779f0.dtsi and r8a779f0-spider.dts,
   9 r8a779f0-s4sk.dts.
  10 - Update Canfd device nodes in device tree R9A779F0.
  11 - Update Source code support canfd device in rcar-canfd.c.
  12
  13 Signed-off-by: Phat Pham <phat.pham.zg@renesas.com>
  14 Signed-off-by: Duy Dang <duy.dang.yw@renesas.com>
  15 ---
  16  arch/arm64/boot/dts/renesas/r8a779f0-s4sk.dts |  28 ++
  17  .../boot/dts/renesas/r8a779f0-spider.dts      | 160 ++++++++++++
  18  arch/arm64/boot/dts/renesas/r8a779f0.dtsi     | 170 +++++++++++-
  19  drivers/net/can/rcar/rcar_can.c               |  28 +-
  20  drivers/net/can/rcar/rcar_canfd.c             | 211 +++++++++++----
  21  drivers/pinctrl/renesas/pfc-r8a779f0.c        | 246 ++++++++++++++++++
  22  6 files changed, 780 insertions(+), 63 deletions(-)
  23
  24 diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f0-s4sk.dts
  25 index b6c61a20cd0d..1288285b5a9d 100644
  26 --- a/arch/arm64/boot/dts/renesas/r8a779f0-s4sk.dts
  27 +++ b/arch/arm64/boot/dts/renesas/r8a779f0-s4sk.dts
  28 @@ -109,6 +109,24 @@ &mmc0 {
  29         status = "okay";
  30  };
  31
  32 +&canfd0 {
  33 +       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
  34 +       pinctrl-names = "default";
  35 +       status = "okay";
  36 +
  37 +       channel0 {
  38 +               status = "okay";
  39 +       };
  40 +
  41 +       channel1 {
  42 +               status = "okay";
  43 +       };
  44 +};
  45 +
  46 +&canfd1 {
  47 +       status = "disabled";
  48 +};
  49 +
  50  &pfc {
  51         pinctrl-0 = <&scif_clk_pins>;
  52         pinctrl-names = "default";
  53 @@ -203,6 +221,16 @@ pins_mdio {
  54                         power-source = <3300>;
  55                 };
  56         };
  57 +
  58 +       canfd0_pins: canfd0 {
  59 +               groups = "canfd0_data";
  60 +               function = "canfd0";
  61 +       };
  62 +
  63 +    canfd1_pins: canfd1 {
  64 +        groups = "canfd1_data";
  65 +        function = "canfd1";
  66 +    };
  67  };
  68
  69  &rwdt {
  70 diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
  71 index 538f413fbffd..0d6b21fe0c07 100644
  72 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
  73 +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
  74 @@ -27,6 +27,86 @@ eeprom@51 {
  75         };
  76  };
  77
  78 +&canfd0 {
  79 +       pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&canfd2_pins>,
  80 +                               <&canfd3_pins>, <&canfd4_pins>, <&canfd5_pins>,
  81 +                               <&canfd6_pins>, <&canfd7_pins>;
  82 +       pinctrl-names = "default";
  83 +       status = "okay";
  84 +
  85 +       channel0 {
  86 +               status = "okay";
  87 +       };
  88 +
  89 +       channel1 {
  90 +               status = "okay";
  91 +       };
  92 +
  93 +       channel2 {
  94 +               status = "okay";
  95 +       };
  96 +
  97 +       channel3 {
  98 +               status = "okay";
  99 +       };
 100 +
 101 +       channel4 {
 102 +               status = "okay";
 103 +       };
 104 +
 105 +       channel5 {
 106 +               status = "okay";
 107 +       };
 108 +
 109 +       channel6 {
 110 +               status = "okay";
 111 +       };
 112 +
 113 +       channel7 {
 114 +               status = "okay";
 115 +       };
 116 +};
 117 +
 118 +&canfd1 {
 119 +       pinctrl-0 = <&canfd8_pins>,<&canfd9_pins>, <&canfd10_pins>,
 120 +                               <&canfd11_pins>, <&canfd12_pins>, <&canfd13_pins>,
 121 +                               <&canfd14_pins>, <&canfd15_pins>;
 122 +       pinctrl-names = "default";
 123 +       status = "okay";
 124 +
 125 +       channel0 {
 126 +               status = "okay";
 127 +       };
 128 +
 129 +       channel1 {
 130 +               status = "okay";
 131 +       };
 132 +
 133 +       channel2 {
 134 +               status = "okay";
 135 +       };
 136 +
 137 +       channel3 {
 138 +               status = "okay";
 139 +       };
 140 +
 141 +       channel4 {
 142 +               status = "okay";
 143 +       };
 144 +
 145 +       channel5 {
 146 +               status = "okay";
 147 +       };
 148 +
 149 +       channel6 {
 150 +               status = "okay";
 151 +       };
 152 +
 153 +       channel7 {
 154 +               status = "okay";
 155 +       };
 156 +};
 157 +
 158  &pfc {
 159         tsn0_pins: tsn0 {
 160                 mux {
 161 @@ -73,6 +153,86 @@ pins_mdio {
 162                 };
 163         };
 164
 165 +       canfd0_pins: canfd0 {
 166 +               groups = "canfd0_data";
 167 +               function = "canfd0";
 168 +       };
 169 +
 170 +       canfd1_pins: canfd1 {
 171 +               groups = "canfd1_data";
 172 +               function = "canfd1";
 173 +       };
 174 +
 175 +       canfd2_pins: canfd2 {
 176 +               groups = "canfd2_data";
 177 +               function = "canfd2";
 178 +       };
 179 +
 180 +       canfd3_pins: canfd3 {
 181 +               groups = "canfd3_data";
 182 +               function = "canfd3";
 183 +       };
 184 +
 185 +       canfd4_pins: canfd4 {
 186 +               groups = "canfd4_data";
 187 +               function = "canfd4";
 188 +       };
 189 +
 190 +       canfd5_pins: canfd5 {
 191 +               groups = "canfd5_data";
 192 +               function = "canfd5";
 193 +       };
 194 +
 195 +       canfd6_pins: canfd6 {
 196 +               groups = "canfd6_data";
 197 +               function = "canfd6";
 198 +       };
 199 +
 200 +       canfd7_pins: canfd7 {
 201 +               groups = "canfd7_data";
 202 +               function = "canfd7";
 203 +       };
 204 +
 205 +       canfd8_pins: canfd8 {
 206 +               groups = "canfd8_data";
 207 +               function = "canfd8";
 208 +       };
 209 +
 210 +       canfd9_pins: canfd9 {
 211 +               groups = "canfd9_data";
 212 +               function = "canfd9";
 213 +       };
 214 +
 215 +       canfd10_pins: canfd10 {
 216 +               groups = "canfd10_data";
 217 +               function = "canfd10";
 218 +       };
 219 +
 220 +       canfd11_pins: canfd11 {
 221 +               groups = "canfd11_data";
 222 +               function = "canfd11";
 223 +       };
 224 +
 225 +       canfd12_pins: canfd12 {
 226 +               groups = "canfd12_data";
 227 +               function = "canfd12";
 228 +       };
 229 +
 230 +       canfd13_pins: canfd13 {
 231 +               groups = "canfd13_data";
 232 +               function = "canfd13";
 233 +       };
 234 +
 235 +       canfd14_pins: canfd14 {
 236 +               groups = "canfd14_data";
 237 +               function = "canfd14";
 238 +       };
 239 +
 240 +       canfd15_pins: canfd15 {
 241 +               groups = "canfd15_data";
 242 +               function = "canfd15";
 243 +       };
 244 +
 245         pcie0_pins: pcie0 {
 246                 groups = "pcie0_clkreq_n";
 247                 function = "pcie";
 248 diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
 249 index ddda2fc3acd0..b930b93ab3f7 100644
 250 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
 251 +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
 252 @@ -23,6 +23,13 @@ aliases {
 253                 i2c5 = &i2c5;
 254         };
 255
 256 +       /* External CAN clock - to be overridden by boards that provide it */
 257 +       can_clk: can {
 258 +               compatible = "fixed-clock";
 259 +               #clock-cells = <0>;
 260 +               clock-frequency = <40000000>;
 261 +       };
 262 +
 263         cluster1_opp: opp_table10 {
 264                 compatible = "operating-points-v2";
 265                 opp-shared;
 266 @@ -329,7 +336,7 @@ pfc: pin-controller@e6050000 {
 267                         compatible = "renesas,pfc-r8a779f0";
 268                         reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
 269                               <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>,
 270 -                             <0 0xdfd90000 0 0x16c>, <0 0xdfd90800 0 0x16c>,
 271 +                                 <0 0xdfd90000 0 0x16c>, <0 0xdfd90800 0 0x16c>,
 272                               <0 0xdfd91000 0 0x16c>, <0 0xdfd91800 0 0x16c>;
 273                 };
 274
 275 @@ -389,6 +396,63 @@ gpio3: gpio@e6051980 {
 276                         resets = <&cpg 915>;
 277                 };
 278
 279 +               /* Porting GPIO GP 4~7 from Control Domain to Application Domain */
 280 +               gpio4: gpio@dfd90180 {
 281 +                       compatible = "renesas,gpio-r8a779f0";
 282 +                       reg = <0 0xdfd90180 0 0x54>;
 283 +                       interrupts = <GIC_SPI 826 IRQ_TYPE_LEVEL_HIGH>;
 284 +                       #gpio-cells = <2>;
 285 +                       gpio-controller;
 286 +                       gpio-ranges = <&pfc 0 128 31>;
 287 +                       #interrupt-cells = <2>;
 288 +                       interrupt-controller;
 289 +                       clocks = <&cpg CPG_MOD 915>;
 290 +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 291 +                       resets = <&cpg 915>;
 292 +               };
 293 +
 294 +               gpio5: gpio@dfd90980 {
 295 +                       compatible = "renesas,gpio-r8a779f0";
 296 +                       reg = <0 0xdfd90980 0 0x54>;
 297 +                       interrupts = <GIC_SPI 827 IRQ_TYPE_LEVEL_HIGH>;
 298 +                       #gpio-cells = <2>;
 299 +                       gpio-controller;
 300 +                       gpio-ranges = <&pfc 0 160 20>;
 301 +                       #interrupt-cells = <2>;
 302 +                       interrupt-controller;
 303 +                       clocks = <&cpg CPG_MOD 915>;
 304 +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 305 +                       resets = <&cpg 915>;
 306 +               };
 307 +
 308 +               gpio6: gpio@dfd91180 {
 309 +                       compatible = "renesas,gpio-r8a779f0";
 310 +                       reg = <0 0xdfd91180 0 0x54>;
 311 +                       interrupts = <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>;
 312 +                       #gpio-cells = <2>;
 313 +                       gpio-controller;
 314 +                       gpio-ranges = <&pfc 0 192 24>;
 315 +                       #interrupt-cells = <2>;
 316 +                       interrupt-controller;
 317 +                       clocks = <&cpg CPG_MOD 915>;
 318 +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 319 +                       resets = <&cpg 915>;
 320 +               };
 321 +
 322 +               gpio7: gpio@dfd91980 {
 323 +                       compatible = "renesas,gpio-r8a779f0";
 324 +                       reg = <0 0xdfd91980 0 0x54>;
 325 +                       interrupts = <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>;
 326 +                       #gpio-cells = <2>;
 327 +                       gpio-controller;
 328 +                       gpio-ranges = <&pfc 0 224 32>;
 329 +                       #interrupt-cells = <2>;
 330 +                       interrupt-controller;
 331 +                       clocks = <&cpg CPG_MOD 915>;
 332 +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 333 +                       resets = <&cpg 915>;
 334 +               };
 335 +
 336                 cpg: clock-controller@e6150000 {
 337                         compatible = "renesas,r8a779f0-cpg-mssr";
 338                         reg = <0 0xe6150000 0 0x4000>;
 339 @@ -410,6 +474,110 @@ sysc: system-controller@e6180000 {
 340                         #power-domain-cells = <1>;
 341                 };
 342
 343 +               canfd0: can@dff50000 {
 344 +                       compatible = "renesas,r8a779f0-canfd";
 345 +                       reg = <0 0xdff50000 0 0x8600>;
 346 +                       interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
 347 +                                        <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
 348 +                                        <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
 349 +                                        <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
 350 +                                        <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
 351 +                                        <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
 352 +                                        <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
 353 +                                        <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
 354 +                                        <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>;
 355 +                       clocks = <&can_clk>;
 356 +                       clock-names = "can_clk";
 357 +                       assigned-clocks = <&can_clk>;
 358 +                       assigned-clock-rates = <40000000>;
 359 +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 360 +                       status = "okay";
 361 +
 362 +                       channel0 {
 363 +                               status = "disabled";
 364 +                       };
 365 +
 366 +                       channel1 {
 367 +                               status = "disabled";
 368 +                       };
 369 +
 370 +                       channel2 {
 371 +                               status = "disabled";
 372 +                       };
 373 +
 374 +                       channel3 {
 375 +                               status = "disabled";
 376 +                       };
 377 +
 378 +                       channel4 {
 379 +                               status = "disabled";
 380 +                       };
 381 +
 382 +                       channel5 {
 383 +                               status = "disabled";
 384 +                       };
 385 +
 386 +                       channel6 {
 387 +                               status = "disabled";
 388 +                       };
 389 +
 390 +                       channel7 {
 391 +                               status = "disabled";
 392 +                       };
 393 +               };
 394 +
 395 +               canfd1: can@dfd00000 {
 396 +                       compatible = "renesas,r8a779f0-canfd";
 397 +                       reg = <0 0xdfd00000 0 0x8600>;
 398 +                       interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
 399 +                                        <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
 400 +                                        <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
 401 +                                        <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
 402 +                                        <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
 403 +                                        <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
 404 +                                        <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>,
 405 +                                        <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
 406 +                                        <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
 407 +                       clocks = <&can_clk>;
 408 +                       clock-names = "can_clk";
 409 +                       assigned-clocks = <&can_clk>;
 410 +                       assigned-clock-rates = <40000000>;
 411 +                       power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 412 +                       status = "okay";
 413 +
 414 +                       channel0 {
 415 +                               status = "disabled";
 416 +                       };
 417 +
 418 +                       channel1 {
 419 +                               status = "disabled";
 420 +                       };
 421 +
 422 +                       channel2 {
 423 +                               status = "disabled";
 424 +                       };
 425 +
 426 +                       channel3 {
 427 +                               status = "disabled";
 428 +                       };
 429 +
 430 +                       channel4 {
 431 +                               status = "disabled";
 432 +                       };
 433 +
 434 +                       channel5 {
 435 +                               status = "disabled";
 436 +                       };
 437 +
 438 +                       channel6 {
 439 +                               status = "disabled";
 440 +                       };
 441 +
 442 +                       channel7 {
 443 +                               status = "disabled";
 444 +                       };
 445 +               };
 446 +
 447                 i2c0: i2c@e6500000 {
 448                         compatible = "renesas,i2c-r8a779f0",
 449                                      "renesas,rcar-gen4-i2c";
 450 diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
 451 index 48575900adb7..134eda66f0dc 100644
 452 --- a/drivers/net/can/rcar/rcar_can.c
 453 +++ b/drivers/net/can/rcar/rcar_can.c
 454 @@ -235,11 +235,8 @@ static void rcar_can_error(struct net_device *ndev)
 455         if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) {
 456                 txerr = readb(&priv->regs->tecr);
 457                 rxerr = readb(&priv->regs->recr);
 458 -               if (skb) {
 459 +               if (skb)
 460                         cf->can_id |= CAN_ERR_CRTL;
 461 -                       cf->data[6] = txerr;
 462 -                       cf->data[7] = rxerr;
 463 -               }
 464         }
 465         if (eifr & RCAR_CAN_EIFR_BEIF) {
 466                 int rx_errors = 0, tx_errors = 0;
 467 @@ -339,6 +336,9 @@ static void rcar_can_error(struct net_device *ndev)
 468                 can_bus_off(ndev);
 469                 if (skb)
 470                         cf->can_id |= CAN_ERR_BUSOFF;
 471 +       } else if (skb) {
 472 +               cf->data[6] = txerr;
 473 +               cf->data[7] = rxerr;
 474         }
 475         if (eifr & RCAR_CAN_EIFR_ORIF) {
 476                 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n");
 477 @@ -846,10 +846,12 @@ static int __maybe_unused rcar_can_suspend(struct device *dev)
 478         struct rcar_can_priv *priv = netdev_priv(ndev);
 479         u16 ctlr;
 480
 481 -       if (netif_running(ndev)) {
 482 -               netif_stop_queue(ndev);
 483 -               netif_device_detach(ndev);
 484 -       }
 485 +       if (!netif_running(ndev))
 486 +               return 0;
 487 +
 488 +       netif_stop_queue(ndev);
 489 +       netif_device_detach(ndev);
 490 +
 491         ctlr = readw(&priv->regs->ctlr);
 492         ctlr |= RCAR_CAN_CTLR_CANM_HALT;
 493         writew(ctlr, &priv->regs->ctlr);
 494 @@ -868,6 +870,9 @@ static int __maybe_unused rcar_can_resume(struct device *dev)
 495         u16 ctlr;
 496         int err;
 497
 498 +       if (!netif_running(ndev))
 499 +               return 0;
 500 +
 501         err = clk_enable(priv->clk);
 502         if (err) {
 503                 netdev_err(ndev, "clk_enable() failed, error %d\n", err);
 504 @@ -881,10 +886,9 @@ static int __maybe_unused rcar_can_resume(struct device *dev)
 505         writew(ctlr, &priv->regs->ctlr);
 506         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 507
 508 -       if (netif_running(ndev)) {
 509 -               netif_device_attach(ndev);
 510 -               netif_start_queue(ndev);
 511 -       }
 512 +       netif_device_attach(ndev);
 513 +       netif_start_queue(ndev);
 514 +
 515         return 0;
 516  }
 517
 518 diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
 519 index b458b5fd7900..e4f820308954 100644
 520 --- a/drivers/net/can/rcar/rcar_canfd.c
 521 +++ b/drivers/net/can/rcar/rcar_canfd.c
 522 @@ -203,7 +203,7 @@
 523  #define RCANFD_FDCFG_FDOE              BIT(28)
 524  #define RCANFD_FDCFG_TDCE              BIT(9)
 525  #define RCANFD_FDCFG_TDCOC             BIT(8)
 526 -#define RCANFD_FDCFG_TDCO(x)           (((x) & 0x7f) >> 16)
 527 +#define RCANFD_FDCFG_TDCO(x)           (((x) & 0xff) << 16)
 528
 529  /* RSCFDnCFDRFCCx */
 530  #define RCANFD_RFCC_RFIM               BIT(12)
 531 @@ -506,6 +506,7 @@
 532  /* R-Car V3U Classical and CAN FD mode specific register map */
 533  #define RCANFD_V3U_CFDCFG              (0x1314)
 534  #define RCANFD_V3U_DCFG(m)             (0x1400 + (0x20 * (m)))
 535 +#define RCANFD_V3U_FDCFG(m)            (0x1404 + (0x20 * (m)))
 536
 537  #define RCANFD_V3U_GAFL_OFFSET         (0x1800)
 538
 539 @@ -574,6 +575,7 @@ struct rcar_canfd_channel {
 540
 541  enum rcar_canfd_chip_id {
 542         R8A779G0,
 543 +       R8A779F0,
 544         R8A779A0,
 545         GEN3,
 546  };
 547 @@ -734,13 +736,17 @@ static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
 548         rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
 549
 550         /* Set the controller into appropriate mode */
 551 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 552 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 553                 if (gpriv->fdmode)
 554 -                       rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_CFDCFG,
 555 -                                          RCANFD_FDCFG_FDOE);
 556 +               {
 557 +                       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
 558 +                               rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_FDCFG(ch),
 559 +                                                  RCANFD_FDCFG_FDOE);
 560 +               }
 561                 else
 562 -                       rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_CFDCFG,
 563 -                                          RCANFD_FDCFG_CLOE);
 564 +                       for_each_set_bit(ch, &gpriv->channels_mask, gpriv->max_channels)
 565 +                               rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_FDCFG(ch),
 566 +                                                  RCANFD_FDCFG_CLOE);
 567         } else {
 568                 if (gpriv->fdmode)
 569                         rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
 570 @@ -801,7 +807,7 @@ static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
 571  }
 572
 573  static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 574 -                                          u32 ch)
 575 +                                          u32 ch, int num_ch_enabled)
 576  {
 577         u32 cfg;
 578         int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
 579 @@ -812,7 +818,7 @@ static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 580         } else {
 581                 /* Get number of Channel 0 rules and adjust */
 582                 cfg = rcar_canfd_read(gpriv->base, RCANFD_V3U_GAFLCFG(ch));
 583 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 584 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 585                         start = ch * num_rules;
 586                 else
 587                         start = RCANFD_GAFLCFG_GETRNC(0, cfg);
 588 @@ -821,24 +827,28 @@ static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 589         /* Enable write access to entry */
 590         page = RCANFD_GAFL_PAGENUM(start);
 591
 592 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 593 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 594 +       {
 595                 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 596                                    (RCANFD_V3U_GAFLECTR_AFLPN(page) |
 597                                         RCANFD_GAFLECTR_AFLDAE));
 598 +       }
 599         else
 600                 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
 601                                    (RCANFD_GAFLECTR_AFLPN(page) |
 602                                         RCANFD_GAFLECTR_AFLDAE));
 603
 604         /* Write number of rules for channel */
 605 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 606 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 607 +       {
 608                 rcar_canfd_set_bit(gpriv->base, RCANFD_V3U_GAFLCFG(ch),
 609                                    RCANFD_V3U_GAFLCFG_SETRNC(ch, num_rules));
 610 +       }
 611         else
 612                 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
 613                                    RCANFD_GAFLCFG_SETRNC(ch, num_rules));
 614
 615 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 616 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 617                 offset = RCANFD_V3U_GAFL_OFFSET;
 618         } else {
 619                 if (gpriv->fdmode)
 620 @@ -848,13 +858,13 @@ static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
 621         }
 622
 623         /* Accept all IDs */
 624 -       rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
 625 +       rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, num_ch_enabled), 0);
 626         /* IDE or RTR is not considered for matching */
 627 -       rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
 628 +       rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, num_ch_enabled), 0);
 629         /* Any data length accepted */
 630 -       rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
 631 +       rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, num_ch_enabled), 0);
 632         /* Place the msg in corresponding Rx FIFO entry */
 633 -       rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, start),
 634 +       rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, num_ch_enabled),
 635                            RCANFD_GAFLP1_GAFLFDP(ridx));
 636
 637         /* Disable write access to page */
 638 @@ -879,10 +889,14 @@ static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
 639
 640         cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
 641                 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
 642 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 643 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 644 +       {
 645                 rcar_canfd_write(gpriv->base, RCANFD_V3U_RFCC(ridx), cfg);
 646 +       }
 647         else
 648 +       {
 649                 rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
 650 +       }
 651  }
 652
 653  static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 654 @@ -904,7 +918,7 @@ static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 655         else
 656                 cfpls = 0;      /* b000 - Max 8 bytes payload */
 657
 658 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 659 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 660                 cfg = (RCANFD_V3U_CFCC_CFTML(cftml) | RCANFD_V3U_CFCC_CFM(cfm) |
 661                         RCANFD_V3U_CFCC_CFIM | RCANFD_V3U_CFCC_CFDC(cfdc) |
 662                         RCANFD_V3U_CFCC_CFPLS(cfpls) | RCANFD_V3U_CFCC_CFTXIE);
 663 @@ -919,8 +933,10 @@ static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
 664         }
 665         if (gpriv->fdmode) {
 666                 /* Clear FD mode specific control/status register */
 667 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 668 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 669 +               {
 670                         addr = RCANFD_V3U_CFFDCSTS(ch, RCANFD_CFFIFO_IDX);
 671 +               }
 672                 else
 673                         addr = RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX);
 674
 675 @@ -938,7 +954,9 @@ static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
 676         /* Global interrupts setup */
 677         ctr = RCANFD_GCTR_MEIE;
 678         if (gpriv->fdmode)
 679 +       {
 680                 ctr |= RCANFD_GCTR_CFMPOFIE;
 681 +       }
 682
 683         rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
 684  }
 685 @@ -1005,7 +1023,7 @@ static void rcar_canfd_global_error(struct net_device *ndev)
 686                 stats->tx_dropped++;
 687         }
 688         if (gerfl & RCANFD_GERFL_MES) {
 689 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 690 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 691                         addr = RCANFD_V3U_CFSTS(ch, RCANFD_CFFIFO_IDX);
 692                 else
 693                         addr = RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX);
 694 @@ -1018,7 +1036,7 @@ static void rcar_canfd_global_error(struct net_device *ndev)
 695                         rcar_canfd_write(priv->base, addr,
 696                                          sts & ~RCANFD_CFSTS_CFMLT);
 697                 }
 698 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 699 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 700                         addr = RCANFD_V3U_RFSTS(ridx);
 701                 else
 702                         addr = RCANFD_RFSTS(ridx);
 703 @@ -1171,8 +1189,10 @@ static void rcar_canfd_tx_done(struct net_device *ndev)
 704         u32 ch = priv->channel;
 705         struct rcar_canfd_global *gpriv = priv->gpriv;
 706
 707 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 708 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 709 +       {
 710                 addr = RCANFD_V3U_CFSTS(ch, RCANFD_CFFIFO_IDX);
 711 +       }
 712         else
 713                 addr = RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX);
 714
 715 @@ -1227,7 +1247,7 @@ static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
 716
 717                 /* Global error interrupts */
 718                 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
 719 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 720 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 721                         if (unlikely(RCANFD_V3U_GERFL_ERR(gpriv, gerfl)))
 722                                 rcar_canfd_global_error(ndev);
 723                 } else {
 724 @@ -1235,7 +1255,7 @@ static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
 725                                 rcar_canfd_global_error(ndev);
 726                 }
 727                 /* Handle Rx interrupts */
 728 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 729 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 730                         addr1 = RCANFD_V3U_RFSTS(ridx);
 731                         addr2 = RCANFD_V3U_RFCC(ridx);
 732                 } else {
 733 @@ -1307,6 +1327,7 @@ static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
 734                 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
 735                 txerr = RCANFD_CSTS_TECCNT(sts);
 736                 rxerr = RCANFD_CSTS_RECCNT(sts);
 737 +
 738                 if (unlikely(RCANFD_CERFL_ERR(cerfl)))
 739                         rcar_canfd_error(ndev, cerfl, txerr, rxerr);
 740
 741 @@ -1316,19 +1337,57 @@ static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
 742                         rcar_canfd_state_change(ndev, txerr, rxerr);
 743
 744                 /* Handle Tx interrupts */
 745 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 746 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 747 +               {
 748                         addr = RCANFD_V3U_CFSTS(ch, RCANFD_CFFIFO_IDX);
 749 +               }
 750                 else
 751 +               {
 752                         addr = RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX);
 753 +               }
 754
 755                 sts = rcar_canfd_read(priv->base, addr);
 756
 757                 if (likely(sts & RCANFD_CFSTS_CFTXIF))
 758 +               {
 759                         rcar_canfd_tx_done(ndev);
 760 +               }
 761         }
 762         return IRQ_HANDLED;
 763  }
 764
 765 +static void rcar_canfd_set_samplepoint(struct net_device *dev)
 766 +{
 767 +       struct rcar_canfd_channel *priv = netdev_priv(dev);
 768 +       u32 ch = priv->channel;
 769 +       u16 tdco;
 770 +       u32 cfg;
 771 +       struct rcar_canfd_global *gpriv = priv->gpriv;
 772 +
 773 +       /* Sample point settings */
 774 +       tdco = 2; /* TDCO = 2Tq */
 775 +
 776 +       /* Transceiver Delay Compensation Offset Configuration */
 777 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 778 +               cfg = (RCANFD_FDCFG_TDCE |
 779 +                          RCANFD_FDCFG_TDCO(tdco));
 780 +               rcar_canfd_set_bit(priv->base, RCANFD_V3U_FDCFG(ch), cfg);
 781 +       }
 782 +}
 783 +
 784 +static void rcar_canfd_unset_samplepoint(struct net_device *dev)
 785 +{
 786 +       struct rcar_canfd_channel *priv = netdev_priv(dev);
 787 +       u32 ch = priv->channel;
 788 +       u32 cfg;
 789 +       struct rcar_canfd_global *gpriv = priv->gpriv;
 790 +
 791 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 792 +               cfg = RCANFD_FDCFG_TDCE; /* Disable TDC */
 793 +               rcar_canfd_clear_bit(priv->base, RCANFD_V3U_FDCFG(ch), cfg);
 794 +       }
 795 +}
 796 +
 797  static void rcar_canfd_set_bittiming(struct net_device *dev)
 798  {
 799         struct rcar_canfd_channel *priv = netdev_priv(dev);
 800 @@ -1342,12 +1401,12 @@ static void rcar_canfd_set_bittiming(struct net_device *dev)
 801         /* Nominal bit timing settings */
 802         brp = bt->brp - 1;
 803         sjw = bt->sjw - 1;
 804 -       tseg1 = bt->prop_seg + bt->phase_seg1 + 1;
 805 +       tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
 806         tseg2 = bt->phase_seg2 - 1;
 807
 808         if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
 809                 /* CAN FD only mode */
 810 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 811 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 812                         cfg = (RCANFD_V3U_NCFG_NTSEG1(tseg1) |
 813                                RCANFD_V3U_NCFG_NBRP(brp) |
 814                                RCANFD_V3U_NCFG_NSJW(sjw) |
 815 @@ -1365,10 +1424,16 @@ static void rcar_canfd_set_bittiming(struct net_device *dev)
 816                 /* Data bit timing settings */
 817                 brp = dbt->brp - 1;
 818                 sjw = dbt->sjw - 1;
 819 -               tseg1 = dbt->prop_seg + dbt->phase_seg1 + 1;
 820 +               tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
 821                 tseg2 = dbt->phase_seg2 - 1;
 822
 823 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 824 +               /* Set Secondary Sample Point for high baud rate */
 825 +               if (brp == 0 && tseg1 <= 5 && tseg2 == 1)
 826 +                       rcar_canfd_set_samplepoint(dev);
 827 +               else
 828 +                       rcar_canfd_unset_samplepoint(dev);
 829 +
 830 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 831                         cfg = (RCANFD_V3U_DCFG_DTSEG1(tseg1) |
 832                                RCANFD_V3U_DCFG_DBRP(brp) |
 833                                RCANFD_V3U_DCFG_DSJW(sjw) |
 834 @@ -1387,7 +1452,7 @@ static void rcar_canfd_set_bittiming(struct net_device *dev)
 835                            brp, sjw, tseg1, tseg2);
 836         } else {
 837                 /* Classical CAN only mode */
 838 -               if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 839 +               if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 840                         cfg = (RCANFD_V3U_NCFG_NTSEG1(tseg1) |
 841                                RCANFD_V3U_NCFG_NBRP(brp) |
 842                                RCANFD_V3U_NCFG_NSJW(sjw) |
 843 @@ -1430,7 +1495,7 @@ static int rcar_canfd_start(struct net_device *ndev)
 844         }
 845
 846         /* Enable Common & Rx FIFO */
 847 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 848 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 849                 addr1 = RCANFD_V3U_CFCC(ch, RCANFD_CFFIFO_IDX);
 850                 addr2 = RCANFD_V3U_RFCC(ridx);
 851         } else {
 852 @@ -1505,7 +1570,7 @@ static void rcar_canfd_stop(struct net_device *ndev)
 853         rcar_canfd_disable_channel_interrupts(priv);
 854
 855         /* Disable Common & Rx FIFO */
 856 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 857 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 858                 addr1 = RCANFD_V3U_CFCC(ch, RCANFD_CFFIFO_IDX);
 859                 addr2 = RCANFD_V3U_RFCC(ridx);
 860         } else {
 861 @@ -1544,7 +1609,9 @@ static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
 862         struct rcar_canfd_global *gpriv = priv->gpriv;
 863
 864         if (can_dropped_invalid_skb(ndev, skb))
 865 +       {
 866                 return NETDEV_TX_OK;
 867 +       }
 868
 869         if (cf->can_id & CAN_EFF_FLAG) {
 870                 id = cf->can_id & CAN_EFF_MASK;
 871 @@ -1554,11 +1621,13 @@ static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
 872         }
 873
 874         if (cf->can_id & CAN_RTR_FLAG)
 875 +       {
 876                 id |= RCANFD_CFID_CFRTR;
 877 +       }
 878
 879         dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
 880
 881 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 882 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 883                 rcar_canfd_write(priv->base,
 884                                  RCANFD_V3U_CFID(ch, RCANFD_CFFIFO_IDX), id);
 885                 rcar_canfd_write(priv->base,
 886 @@ -1622,7 +1691,7 @@ static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
 887         /* Start Tx: Write 0xff to CFPC to increment the CPU-side
 888          * pointer for the Common FIFO
 889          */
 890 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 891 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 892                 addr = RCANFD_V3U_CFPCTR(ch, RCANFD_CFFIFO_IDX);
 893         else
 894                 addr = RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX);
 895 @@ -1630,6 +1699,7 @@ static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
 896         rcar_canfd_write(priv->base, addr, 0xff);
 897
 898         spin_unlock_irqrestore(&priv->tx_lock, flags);
 899 +
 900         return NETDEV_TX_OK;
 901  }
 902
 903 @@ -1643,7 +1713,7 @@ static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
 904         u32 ridx = ch + RCANFD_RFFIFO_IDX;
 905         struct rcar_canfd_global *gpriv = priv->gpriv;
 906
 907 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 908 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 909                 id = rcar_canfd_read(priv->base, RCANFD_V3U_RFID(ridx));
 910                 dlc = rcar_canfd_read(priv->base, RCANFD_V3U_RFPTR(ridx));
 911                 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
 912 @@ -1707,7 +1777,7 @@ static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
 913                         if (sts & RCANFD_RFFDSTS_RFBRS)
 914                                 cf->flags |= CANFD_BRS;
 915
 916 -                       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 917 +                       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 918                                 rcar_canfd_get_data(priv, cf,
 919                                                     RCANFD_V3U_RFDF(ridx, 0));
 920                         else
 921 @@ -1719,7 +1789,7 @@ static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
 922                 if (id & RCANFD_RFID_RFRTR)
 923                         cf->can_id |= CAN_RTR_FLAG;
 924                 else
 925 -                       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 926 +                       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 927                                 rcar_canfd_get_data(priv, cf,
 928                                                     RCANFD_V3U_RFDF(ridx, 0));
 929                         else
 930 @@ -1730,7 +1800,7 @@ static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
 931         /* Write 0xff to RFPC to increment the CPU-side
 932          * pointer of the Rx FIFO
 933          */
 934 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0))
 935 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0)
 936                 rcar_canfd_write(priv->base, RCANFD_V3U_RFPCTR(ridx), 0xff);
 937         else
 938                 rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
 939 @@ -1752,7 +1822,7 @@ static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
 940         u32 ridx = ch + RCANFD_RFFIFO_IDX, addr1, addr2;
 941         struct rcar_canfd_global *gpriv = priv->gpriv;
 942
 943 -       if ((gpriv->chip_id == R8A779A0) || (gpriv->chip_id == R8A779G0)) {
 944 +       if (gpriv->chip_id == R8A779A0 || gpriv->chip_id == R8A779G0 || gpriv->chip_id == R8A779F0) {
 945                 addr1 = RCANFD_V3U_RFSTS(ridx);
 946                 addr2 = RCANFD_V3U_RFCC(ridx);
 947         } else {
 948 @@ -1867,15 +1937,15 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
 949
 950         netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
 951                        RCANFD_NAPI_WEIGHT);
 952 +       spin_lock_init(&priv->tx_lock);
 953 +       devm_can_led_init(ndev);
 954 +       gpriv->ch[priv->channel] = priv;
 955         err = register_candev(ndev);
 956         if (err) {
 957                 dev_err(&pdev->dev,
 958                         "register_candev() failed, error %d\n", err);
 959                 goto fail_candev;
 960         }
 961 -       spin_lock_init(&priv->tx_lock);
 962 -       devm_can_led_init(ndev);
 963 -       gpriv->ch[priv->channel] = priv;
 964         dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
 965         return 0;
 966
 967 @@ -1904,7 +1974,8 @@ static int rcar_canfd_probe(struct platform_device *pdev)
 968         struct rcar_canfd_global *gpriv;
 969         struct device_node *of_child;
 970         unsigned long channels_mask = 0;
 971 -       int err, ch_irq, g_irq, i;
 972 +       int err, g_irq, ch_irq, i, num_ch_enabled = 0;
 973 +       int ch_irq_s4[RCANFD_NUM_CHANNELS] = {0, 0, 0, 0, 0, 0, 0, 0};
 974         bool fdmode = true;                     /* CAN FD only mode - default */
 975         const struct rcar_canfd_of_data *of_data;
 976         char *name[RCANFD_NUM_CHANNELS] = {
 977 @@ -1925,13 +1996,28 @@ static int rcar_canfd_probe(struct platform_device *pdev)
 978                         channels_mask |= BIT(i);        /* Channel i */
 979         }
 980
 981 -       ch_irq = platform_get_irq(pdev, 0);
 982 +       /*      ch_irq = platform_get_irq(pdev, 0);
 983         if (ch_irq < 0) {
 984                 err = ch_irq;
 985                 goto fail_dev;
 986         }
 987
 988         g_irq = platform_get_irq(pdev, 1);
 989 +       if (g_irq < 0) {
 990 +               err = g_irq;
 991 +               goto fail_dev;
 992 +       } */
 993 +
 994 +       /* Porting for R8A779F0 */
 995 +       for (i = 0; i < RCANFD_NUM_CHANNELS; i++) {
 996 +               ch_irq_s4[i] = platform_get_irq(pdev, i + 1);
 997 +               if (ch_irq_s4[i] < 0) {
 998 +                       err = ch_irq_s4[i];
 999 +                       goto fail_dev;
1000 +               }
1001 +       }
1002 +
1003 +       g_irq = platform_get_irq(pdev, 0);
1004         if (g_irq < 0) {
1005                 err = g_irq;
1006                 goto fail_dev;
1007 @@ -1950,13 +2036,14 @@ static int rcar_canfd_probe(struct platform_device *pdev)
1008         gpriv->max_channels = of_data->max_channels;
1009
1010         /* Peripheral clock */
1011 -       gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1012 +       /* Porting for R8A779F0, not use fck */
1013 +       /* gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1014         if (IS_ERR(gpriv->clkp)) {
1015                 err = PTR_ERR(gpriv->clkp);
1016                 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1017                         err);
1018                 goto fail_dev;
1019 -       }
1020 +       } */
1021
1022         /* fCAN clock: Pick External clock. If not available fallback to
1023          * CANFD clock
1024 @@ -1971,15 +2058,16 @@ static int rcar_canfd_probe(struct platform_device *pdev)
1025                         goto fail_dev;
1026                 }
1027                 gpriv->fcan = RCANFD_CANFDCLK;
1028 -
1029         } else {
1030                 gpriv->fcan = RCANFD_EXTCLK;
1031         }
1032         fcan_freq = clk_get_rate(gpriv->can_clk);
1033
1034         if (gpriv->fcan == RCANFD_CANFDCLK)
1035 +       {
1036                 /* CANFD clock is further divided by (1/2) within the IP */
1037                 fcan_freq /= 2;
1038 +       }
1039
1040         addr = devm_platform_ioremap_resource(pdev, 0);
1041         if (IS_ERR(addr)) {
1042 @@ -1989,14 +2077,27 @@ static int rcar_canfd_probe(struct platform_device *pdev)
1043         gpriv->base = addr;
1044
1045         /* Request IRQ that's common for both channels */
1046 -       err = devm_request_irq(&pdev->dev, ch_irq,
1047 -                              rcar_canfd_channel_interrupt, 0,
1048 -                              "canfd.chn", gpriv);
1049 +       /*      err = devm_request_irq(&pdev->dev, ch_irq,
1050 +                               rcar_canfd_channel_interrupt, 0,
1051 +                               "canfd.chn", gpriv);
1052         if (err) {
1053                 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1054                         ch_irq, err);
1055                 goto fail_dev;
1056 +       } */
1057 +
1058 +       /* Porting for R8A779F0 */
1059 +       for (i = 0; i < RCANFD_NUM_CHANNELS; i++) {
1060 +               err = devm_request_irq(&pdev->dev, ch_irq_s4[i],
1061 +                                       rcar_canfd_channel_interrupt, 0,
1062 +                                       "canfd.chn", gpriv);
1063 +               if (err) {
1064 +                       dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1065 +                               ch_irq_s4[i], err);
1066 +                       goto fail_dev;
1067 +               }
1068         }
1069 +
1070         err = devm_request_irq(&pdev->dev, g_irq,
1071                                rcar_canfd_global_interrupt, 0,
1072                                "canfd.gbl", gpriv);
1073 @@ -2032,7 +2133,8 @@ static int rcar_canfd_probe(struct platform_device *pdev)
1074                 rcar_canfd_configure_tx(gpriv, ch);
1075
1076                 /* Configure receive rules */
1077 -               rcar_canfd_configure_afl_rules(gpriv, ch);
1078 +               rcar_canfd_configure_afl_rules(gpriv, ch, num_ch_enabled);
1079 +               num_ch_enabled++;
1080         }
1081
1082         /* Configure common interrupts */
1083 @@ -2109,6 +2211,11 @@ static const struct rcar_canfd_of_data of_rcanfd_v4h_compatible = {
1084         .max_channels = 8,
1085  };
1086
1087 +static const struct rcar_canfd_of_data of_rcanfd_s4_compatible = {
1088 +       .chip_id = R8A779F0,
1089 +       .max_channels = 8,
1090 +};
1091 +
1092  static const struct rcar_canfd_of_data of_rcanfd_v3u_compatible = {
1093         .chip_id = R8A779A0,
1094         .max_channels = 8,
1095 @@ -2124,6 +2231,10 @@ static const struct of_device_id rcar_canfd_of_table[] = {
1096                 .compatible = "renesas,r8a779g0-canfd",
1097                 .data = &of_rcanfd_v4h_compatible,
1098         },
1099 +       {
1100 +               .compatible = "renesas,r8a779f0-canfd",
1101 +               .data = &of_rcanfd_s4_compatible,
1102 +       },
1103         {
1104                 .compatible = "renesas,r8a779a0-canfd",
1105                 .data = &of_rcanfd_v3u_compatible,
1106 diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
1107 index de01d4d6b1b1..822b4f7e450f 100644
1108 --- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
1109 +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
1110 @@ -11,8 +11,10 @@
1111  #include <linux/io.h>
1112  #include <linux/kernel.h>
1113
1114 +#include "core.h"
1115  #include "sh_pfc.h"
1116
1117 +#define ENABLE_ACCESS_TO_CONTROL_DOMAIN
1118  #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
1119
1120  #define CPU_ALL_GP(fn, sfx)    \
1121 @@ -1170,6 +1172,150 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1122         PINMUX_GPIO_GP_ALL(),
1123  };
1124
1125 +/* - CANFD0 ----------------------------------------------------------------- */
1126 +static const unsigned int canfd0_data_pins[] = {
1127 +       /* CANFD0_TX, CANFD0_RX */
1128 +       RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
1129 +};
1130 +static const unsigned int canfd0_data_mux[] = {
1131 +       CAN0TX_MARK, CAN0RX_INTP0_MARK,
1132 +};
1133 +
1134 +/* - CANFD1 ----------------------------------------------------------------- */
1135 +static const unsigned int canfd1_data_pins[] = {
1136 +       /* CANFD1_TX, CANFD1_RX */
1137 +       RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1138 +};
1139 +static const unsigned int canfd1_data_mux[] = {
1140 +       CAN1TX_MARK, CAN1RX_INTP1_MARK,
1141 +};
1142 +
1143 +/* - CANFD2 ----------------------------------------------------------------- */
1144 +static const unsigned int canfd2_data_pins[] = {
1145 +       /* CANFD2_TX, CANFD2_RX */
1146 +       RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1147 +};
1148 +static const unsigned int canfd2_data_mux[] = {
1149 +       CAN2TX_MARK, CAN2RX_INTP2_MARK,
1150 +};
1151 +
1152 +/* - CANFD3 ----------------------------------------------------------------- */
1153 +static const unsigned int canfd3_data_pins[] = {
1154 +       /* CANFD2_TX, CANFD2_RX */
1155 +       RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1156 +};
1157 +static const unsigned int canfd3_data_mux[] = {
1158 +       CAN3TX_MARK, CAN3RX_INTP3_MARK,
1159 +};
1160 +
1161 +/* - CANFD4 ----------------------------------------------------------------- */
1162 +static const unsigned int canfd4_data_pins[] = {
1163 +       /* CANFD4_TX, CANFD4_RX */
1164 +       RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1165 +};
1166 +static const unsigned int canfd4_data_mux[] = {
1167 +       CAN4TX_MARK, CAN4RX_INTP4_MARK,
1168 +};
1169 +
1170 +/* - CANFD5 ----------------------------------------------------------------- */
1171 +static const unsigned int canfd5_data_pins[] = {
1172 +       /* CANFD5_TX, CANFD5_RX */
1173 +       RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1174 +};
1175 +static const unsigned int canfd5_data_mux[] = {
1176 +       CAN5TX_MARK, CAN5RX_INTP5_MARK,
1177 +};
1178 +
1179 +/* - CANFD6 ----------------------------------------------------------------- */
1180 +static const unsigned int canfd6_data_pins[] = {
1181 +       /* CANFD6_TX, CANFD6_RX */
1182 +       RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1183 +};
1184 +static const unsigned int canfd6_data_mux[] = {
1185 +       CAN6TX_MARK, CAN6RX_INTP6_MARK,
1186 +};
1187 +
1188 +/* - CANFD7 ----------------------------------------------------------------- */
1189 +static const unsigned int canfd7_data_pins[] = {
1190 +       /* CANFD7_TX, CANFD7_RX */
1191 +       RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1192 +};
1193 +static const unsigned int canfd7_data_mux[] = {
1194 +       CAN7TX_MARK, CAN7RX_INTP7_MARK,
1195 +};
1196 +
1197 +/* - CANFD8 ----------------------------------------------------------------- */
1198 +static const unsigned int canfd8_data_pins[] = {
1199 +       /* CANFD8_TX, CANFD8_RX */
1200 +       RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 17),
1201 +};
1202 +static const unsigned int canfd8_data_mux[] = {
1203 +       CAN8TX_MARK, CAN8RX_INTP8_MARK,
1204 +};
1205 +
1206 +/* - CANFD9 ----------------------------------------------------------------- */
1207 +static const unsigned int canfd9_data_pins[] = {
1208 +       /* CANFD9_TX, CANFD9_RX */
1209 +       RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 19),
1210 +};
1211 +static const unsigned int canfd9_data_mux[] = {
1212 +       CAN9TX_MARK, CAN9RX_INTP9_MARK,
1213 +};
1214 +
1215 +/* - CANFD10 ----------------------------------------------------------------- */
1216 +static const unsigned int canfd10_data_pins[] = {
1217 +       /* CANFD10_TX, CANFD10_RX */
1218 +       RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 21),
1219 +};
1220 +static const unsigned int canfd10_data_mux[] = {
1221 +       CAN10TX_MARK, CAN10RX_INTP10_MARK,
1222 +};
1223 +
1224 +/* - CANFD11 ----------------------------------------------------------------- */
1225 +static const unsigned int canfd11_data_pins[] = {
1226 +       /* CANFD11_TX, CANFD11_RX */
1227 +       RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 23),
1228 +};
1229 +static const unsigned int canfd11_data_mux[] = {
1230 +       CAN11TX_MARK, CAN11RX_INTP11_MARK,
1231 +};
1232 +
1233 +/* - CANFD12 ----------------------------------------------------------------- */
1234 +static const unsigned int canfd12_data_pins[] = {
1235 +       /* CANFD12_TX, CANFD12_RX */
1236 +       RCAR_GP_PIN(7, 24), RCAR_GP_PIN(7, 25),
1237 +};
1238 +static const unsigned int canfd12_data_mux[] = {
1239 +       CAN12TX_MARK, CAN12RX_INTP12_MARK,
1240 +};
1241 +
1242 +/* - CANFD13 ----------------------------------------------------------------- */
1243 +static const unsigned int canfd13_data_pins[] = {
1244 +       /* CANFD13_TX, CANFD13_RX */
1245 +       RCAR_GP_PIN(7, 26), RCAR_GP_PIN(7, 27),
1246 +};
1247 +static const unsigned int canfd13_data_mux[] = {
1248 +       CAN13TX_MARK, CAN13RX_INTP13_MARK,
1249 +};
1250 +
1251 +/* - CANFD14 ----------------------------------------------------------------- */
1252 +static const unsigned int canfd14_data_pins[] = {
1253 +       /* CANFD14_TX, CANFD14_RX */
1254 +       RCAR_GP_PIN(7, 28), RCAR_GP_PIN(7, 29),
1255 +};
1256 +static const unsigned int canfd14_data_mux[] = {
1257 +       CAN14TX_MARK, CAN14RX_INTP14_MARK,
1258 +};
1259 +
1260 +/* - CANFD15 ----------------------------------------------------------------- */
1261 +static const unsigned int canfd15_data_pins[] = {
1262 +       /* CANFD15_TX, CANFD15_RX */
1263 +       RCAR_GP_PIN(7, 30), RCAR_GP_PIN(7, 31),
1264 +};
1265 +static const unsigned int canfd15_data_mux[] = {
1266 +       CAN15TX_MARK, CAN15RX_INTP15_MARK,
1267 +};
1268 +
1269  /* - TSN0 ------------------------------------------------ */
1270  static const unsigned int tsn0_link_pins[] = {
1271         /* TSN0_LINK */
1272 @@ -1893,6 +2039,88 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1273         SH_PFC_PIN_GROUP(taud1_pwm5),
1274         SH_PFC_PIN_GROUP(taud1_pwm6),
1275         SH_PFC_PIN_GROUP(taud1_pwm7),
1276 +
1277 +       SH_PFC_PIN_GROUP(canfd0_data),
1278 +       SH_PFC_PIN_GROUP(canfd1_data),
1279 +       SH_PFC_PIN_GROUP(canfd2_data),
1280 +       SH_PFC_PIN_GROUP(canfd3_data),
1281 +       SH_PFC_PIN_GROUP(canfd4_data),
1282 +       SH_PFC_PIN_GROUP(canfd5_data),
1283 +       SH_PFC_PIN_GROUP(canfd6_data),
1284 +       SH_PFC_PIN_GROUP(canfd7_data),
1285 +
1286 +       SH_PFC_PIN_GROUP(canfd8_data),
1287 +       SH_PFC_PIN_GROUP(canfd9_data),
1288 +       SH_PFC_PIN_GROUP(canfd10_data),
1289 +       SH_PFC_PIN_GROUP(canfd11_data),
1290 +       SH_PFC_PIN_GROUP(canfd12_data),
1291 +       SH_PFC_PIN_GROUP(canfd13_data),
1292 +       SH_PFC_PIN_GROUP(canfd14_data),
1293 +       SH_PFC_PIN_GROUP(canfd15_data),
1294 +};
1295 +
1296 +static const char * const canfd0_groups[] = {
1297 +       "canfd0_data",
1298 +};
1299 +
1300 +static const char * const canfd1_groups[] = {
1301 +       "canfd1_data",
1302 +};
1303 +
1304 +static const char * const canfd2_groups[] = {
1305 +       "canfd2_data",
1306 +};
1307 +
1308 +static const char * const canfd3_groups[] = {
1309 +       "canfd3_data",
1310 +};
1311 +
1312 +static const char * const canfd4_groups[] = {
1313 +       "canfd4_data",
1314 +};
1315 +
1316 +static const char * const canfd5_groups[] = {
1317 +       "canfd5_data",
1318 +};
1319 +
1320 +static const char * const canfd6_groups[] = {
1321 +       "canfd6_data",
1322 +};
1323 +
1324 +static const char * const canfd7_groups[] = {
1325 +       "canfd7_data",
1326 +};
1327 +
1328 +static const char * const canfd8_groups[] = {
1329 +       "canfd8_data",
1330 +};
1331 +
1332 +static const char * const canfd9_groups[] = {
1333 +       "canfd9_data",
1334 +};
1335 +
1336 +static const char * const canfd10_groups[] = {
1337 +       "canfd10_data",
1338 +};
1339 +
1340 +static const char * const canfd11_groups[] = {
1341 +       "canfd11_data",
1342 +};
1343 +
1344 +static const char * const canfd12_groups[] = {
1345 +       "canfd12_data",
1346 +};
1347 +
1348 +static const char * const canfd13_groups[] = {
1349 +       "canfd13_data",
1350 +};
1351 +
1352 +static const char * const canfd14_groups[] = {
1353 +       "canfd14_data",
1354 +};
1355 +
1356 +static const char * const canfd15_groups[] = {
1357 +       "canfd15_data",
1358  };
1359
1360  static const char * const tsn0_groups[] = {
1361 @@ -2050,6 +2278,24 @@ static const char * const taud1_pwm_groups[] = {
1362  };
1363
1364  static const struct sh_pfc_function pinmux_functions[] = {
1365 +       SH_PFC_FUNCTION(canfd0),
1366 +       SH_PFC_FUNCTION(canfd1),
1367 +       SH_PFC_FUNCTION(canfd2),
1368 +       SH_PFC_FUNCTION(canfd3),
1369 +       SH_PFC_FUNCTION(canfd4),
1370 +       SH_PFC_FUNCTION(canfd5),
1371 +       SH_PFC_FUNCTION(canfd6),
1372 +       SH_PFC_FUNCTION(canfd7),
1373 +
1374 +       SH_PFC_FUNCTION(canfd8),
1375 +       SH_PFC_FUNCTION(canfd9),
1376 +       SH_PFC_FUNCTION(canfd10),
1377 +       SH_PFC_FUNCTION(canfd11),
1378 +       SH_PFC_FUNCTION(canfd12),
1379 +       SH_PFC_FUNCTION(canfd13),
1380 +       SH_PFC_FUNCTION(canfd14),
1381 +       SH_PFC_FUNCTION(canfd15),
1382 +
1383         SH_PFC_FUNCTION(tsn0),
1384         SH_PFC_FUNCTION(tsn1),
1385         SH_PFC_FUNCTION(tsn2),
1386 --
1387 2.25.1
1388